EEWORLDEEWORLDEEWORLD

Part Number

Search
 PDF

36440MF087

Description
六角支座 有螺纹 #4-40 尼龙 0.875"(22.23mm)7/8" 天然
Categoryaccessories    hardware-fastener   
ManufacturerEssentra Components
Environmental Compliance
Download Datasheet Parametric View All

36440MF087 Online Shopping

Suppliers Part Number Price MOQ In stock  
36440MF087 - - View Buy Now

36440MF087 Overview

六角支座 有螺纹 #4-40 尼龙 0.875"(22.23mm)7/8" 天然

36440MF087 Parametric

Parameter NameAttribute value
category
MakerEssentra Components
seriesMicroPlastics
PackageBulk
typeHexagonal support
有螺纹/无螺纹Threaded
genderMale head, female head
螺钉、螺纹规格#4-40
Diameter - Internal-
Diameter - External0.250"(6.35mm)1/4" 六角形
Height between panels0.875"(22.23mm)7/8"
长度 - 总体1.063"(26.99mm)
characteristic-
Materialnylon
plating-
colornatural
weight-
Basic product number36440MF
Ask a question about driving LED
I use the PWM output of the microcontroller to drive two LEDs alternately, because I don't want to use DA. One of the LEDs requires a voltage of 2.4V to light up, and the other requires 1.5V. How can ...
beijilang5 Embedded System
The circuit exploded, haha
Today, a customer came from Japan and brought a circuit board to Shenzhen for debugging. I looked at the circuit diagram and saw that the ground of the 5V power supply and the 220V are the same ground...
jxb01033016 Talking
Is the clock constraint hold of ispLEVER handled the same as that of xilinx?
In the tutorial of ispLEVER , there is no instruction on how to deal with the clock constraint hold in the spreadsheet . It is always blank. Question: 1/ Is the clock constraint hold of ispLEVER handl...
eeleader FPGA/CPLD
How to use VS2005 to develop applications running on winCE5.0
How to use VS2005 to develop applications running on winCE5.0...
zjl2050 Embedded System
Help solve vhdl:quartus7.2 problem encountered when running if..genarate
本人在quartus7.2运行如下vhdl代码: library ieee;use ieee.std_logic_1164.all;entity shift isgeneric (len:integer);port(a,clk:in std_logic;b:out std_logic);end shift;architecture behav of shift iscomponent dffpor...
kittenqq Embedded System
Thinking about whether the result of FPGA compilation can be converted into source code?
1. Can the .POF and .SOF files compiled by FPGA be converted to VHDL or VERILOG? Or can the .JED files compiled by XILINX be converted to VHDL or VERILOG? I think if this problem can be reversed, it s...
eeleader FPGA/CPLD

EEWorld
subscription
account

EEWorld
service
account

Automotive
development
circle

Robot
development
community

Index Files: 1753  278  1029  2219  1455  36  6  21  45  30 
Datasheet   0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
Room 1530, 15th Floor, Building B, No. 18 Zhongguancun Street, Haidian District, Beijing Telephone: (010) 82350740 Postal Code: 100190
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved 京ICP证060456号 京ICP备10001474号-1 电信业务审批[2006]字第258号函 京公网安备 11010802033920号