FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-13707-3E
16-bit Proprietary Microcontroller
CMOS
F
2
MC-16LX MB90520A/520B Series
MB90522A/523A/522B/523B/F523B/V520A
s
DESCRIPTION
The MB90520A/520B series is a general-purpose 16-bit microcontroller designed for process control applications
in consumer products that require high-speed real-time processing.
The microcontroller instruction set is based on the AT architecture of the F
2
MC
*
family with additional instructions
for high-level languages, extended addressing modes, enhanced multiplication and division instructions, and a
complete range of bit manipulation instructions. The microcontroller has a 32-bit accumulator for processing long
word (32-bit) data.
The MB90520A/520B series peripheral resources include an 8/10-bit A/D converter, 8-bit D/A converter, UART
(SCI) , extended I/O serial interfaces 0 and 1, 8/16-bit up/down counter/timers 0 and 1, 8/16-bit PPG timers 0 and
1, a range of I/O timers (16-bit free-run timers 1 and 2, input capture (ICU) 0 and 1, and output compare (OCU)
0 and 1) , an LCD controller/driver, 8 external interrupt inputs, and 8 wakeup interrupts.
* : F
2
MC stands for FUJITSU Flexible MicroController, a registered trademark of FUJITSU LIMITED.
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FEATURES
• Clock
• Internal PLL clock multiplication circuit
• Selectable machine clock (PLL clock) : Base oscillation divided by two or multiplied by one to four
(For a 4 MHz base oscillation, the machine clock range is 4 MHz to 16 MHz) .
(Continued)
120-pin, Plastic, LQFP
120-pin, Plastic, QFP
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PACKAGES
(FPT-120P-M05)
(FPT-120P-M13)
MB90520A/520B Series
(Continued)
• Sub-clock (32.768 KHz) operation available
Minimum instruction execution time : 62.5 ns (for oscillation
=
4 MHz, PLL clock setting
= ×4,
V
CC
=
5.0 V)
•
16MB CPU memory space
Internal 24-bit addressing
•
Instruction set optimized for controller applications
Rich data types (bit, byte, word, long-word)
Extended addressing modes (23 types)
Enhanced signed multiplication and division instructions and RETI instruction
Enhanced calculation precision using a 32-bit accumulator
•
Instruction set designed for high-level language
(C)
and multi-tasking
System stack pointer
Enhanced pointer-indirect instructions and barrel shift instructions
•
Faster execution speed
4-byte instruction queue
ROM mirror function (48 Kbytes of bank FF is mirrored in bank 00)
•
Program patch function
:
An address match detection function
(2
×
addresses)
•
Interrupt function
32 programmable interrupts with 8 levels
•
Automatic data transmission function independent of CPU operation
Extended intelligent I/O service function (EI
2
OS) : Up to 16 channels
•
Low-power consumption
(stand-by)
modes
Sleep mode (CPU operating clock stops, peripherals continue to operate.)
Pseudo-clock mode (Only oscillation clock and timebase timer continue to operate.)
Clock mode (Main oscillation clock stops, sub-clock and clock timer continue to operate.)
Stop mode (Main oscillation and sub-clock both stop.)
CPU intermittent operation mode
Hardware stand-by mode (Change to stop mpde by operating hardware stand-by pins.)
•
Process
CMOS technology
•
I/O ports
General-purpose I/O ports (CMOS input/output) : 53 ports
General-purpose I/O ports (inputs with pull-up resistors) : 24 ports
General-purpose I/O ports (Nch open-drain outputs) : 8 ports
•
Timers
Timebase timer, clock timer, watchdog timer : 1 channel each
8/16-bit PPG timers 0 and 1 : 8-bit
×
2 channels or 16-bit
×
1 channel
16-bit reload timers 0 and 1 : 2 channels
16-bit I/O timers :
16-bit free-run timers 0 and 1 : 2 channels
16-bit input capture 0 : 2 channels (2 channels per unit)
16-bit output compare 0 and 1 : 8 channels (4 channels per unit)
8/16-bit up/down counter/timers 0 and 1 : 8-bit
×
2 channels or 16-bit
×
1 channel
Clock output function : 1 channel
•
Communications macro
(communication
interface)
Extended I/O serial interfaces 0 and 1 : 2 channels
UART (full-duplex, double-buffered, SCI : Can also be used for synchronous serial transfer) : 1 channel
2
MB90520A/520B Series
•
External event interrupt control function
DTP/external interrupts : 8 channels (Can be set to detect rising edges, falling edges, “H” levels, or “L” levels)
Wake-up interrupts : 8 channels (Detects “L” levels only)
Delayed interrupt generation module : 1 channel (for task switching)
•
Analog/digital conversion
8/10-bit A/D converter : 8 channels (Can be initiated by an external trigger. Minimum conversion time
=
10.2
µs
for a 16 MHz machine clock)
8-bit D/A converter : 2 channels (R-2R type. Settling time
=
12.5
µs
for a 16 MHz machine clock)
•
Display function
LCD controller/driver : 32
×
segment drivers
+
4
×
common drivers
•
Other
Supports serial writing to flash memory. (Only on versions with on-board flash memory.)
Note : The MB90520A and 520B series cannot be used in external bus mode. Always set these devices to single-
chip mode.
3
MB90520A/520B Series
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PRODUCT LINEUP
Part
Number MB90522A
Parameter
Classification
ROM size
RAM size
Separate emulator
power supply
*1
Process
Operating power
supply voltage
*2
Internal regulator circuit
3.0 V to 5.5 V
not mounted
Number of instructions : 340
Instruction sizes : 8-bit, 16-bit
Instruction length : 1 byte to 7 bytes
Data sizes : 1-bit, 8-bit, 16-bit
Minimum instruction execution time : 62.5 ns (for a 16 MHz machine clock)
Interrupt processing time : 1.5
µs
min. (for a 16 MHz machine clock)
Low power operation
(standby modes)
Sleep mode, clock mode, pseudo-clock mode, stop mode, hardware standby mode,
and CPU intermittent operation mode
General-purpose I/O ports (CMOS outputs) : 53
General-purpose I/O ports (inputs with pull-up resistors) : 24
General-purpose I/O ports (Nch open drain outputs) : 8
Total : 85
18-bit counter
Interrupt interval : 1.024 ms, 4.096 ms, 16.384 ms, 131.072 ms
(for a 4 MHz base oscillation)
Reset trigger period
•
For a 4 MHz base oscillation : 3.58, 14.33, 57.23, 458.75 ms
•
For 32.768 sub-clock operation : 0.438, 3.500, 7.000, 14.000 s
Number of channels : 2
Generates an interrupt on overflow
Number of channels : 8
Pin change timing : Free run timer register value equals output compare register value.
Number of channels : 2
Saves the value of the freerun timer register when a pin input occurs (rising edge, falling
edge, either edge) .
Number of channels : 2
Count clock frequency : 0.125, 0.5, or 2.0
µs
for a 16 MHz machine clock
Can be used to count an external event clock.
64 Kbytes
Mask ROM
128 Kbytes
64 Kbytes
4 Kbytes
CMOS
2.7 V to 5.5 V
3.0 V to 5.5 V
mounted
128 Kbytes
Flash ROM
128 Kbytes
Evaluation
product
6 Kbytes
No
MB90523A
MB90522B
MB90523B
MB90F523B MB90V520A
CPU functions
I/O ports
Timebase timer
Watchdog timer
16-bit
freerun
timer
16-bit
I/O
timers
16-bit
output
compare
16-bit
input
capture
16-bit reload timer
(Continued)
4
MB90520A/520B Series
(Continued)
Part
Number
Parameter
Clock timer
8/16-bit PPG timer
8/16 -bit up/down
counter/timers
Clock monitor
Delayed interrupt
generation module
DTP/External
interrupts
15-bit timer
Interrupt interval : 0.438, 0.5, or 2.0
µs
for sub-clock frequency
=
32.768 kHz
Number of channels : 1 (Can be used in 2
×
8-bit channel mode)
Can generate a pulse waveform output with specified period and 0 to 100% duty ratio.
Number of channels : 1 (Can be used in 2
×
8-bit channel mode)
External event inputs : 6 channels
Reload/compare function : 8-bit
×
2 channels
Clock output frequency : Machine clock/2
1
to machine clock/2
8
Interrupt generation module for task switching. (Used by REALOS.)
Input channels : 8
Generates interrupts to the CPU on rising edges, falling edges with input “H” level, or “L”
level.
Can be used for external event interrupts and to activate EI
2
OS.
Input channels : 8
Triggered by “L” level.
Number of channels : 8
Resolution : 8-bit or 10-bit selectable
Conversion can be performed sequentially for multiple consecutive channels.
•
Single-shot conversion mode : Converts specified channel once only.
•
Continuous conversion mode : Repeatedly converts specified channel.
•
Intermittent conversion mode : Converts specified channel then halts temporarily.
Number of channels : 2
Resolution : 8-bit
Number of channels : 1
Clock synchronous transfer : 62.5 Kbps to 1 Mbps
Clock asynchronous transfer : 1202 bps to 31250 bps
Supports bi-directional and master-slave communications.
Number of channels : 2
Clock synchronous transfer : 31.25 Kbps to 1 Mbps (Using internal shift clock)
Transmission format : Selectable LSB-first or MSB-first
Number of common outputs : 4
Number of segment outputs : 32
Number of power supply pins for LCD drive : 4
LCD display memory : 16 bytes
Divider resistor for LCD drive : Internal
MB90522A
MB90523A
MB90522B
MB90523B
MB90F523B MB90V520A
Wakeup interrupts
8/10-bit A/D converter
(successive
approximation type)
8-bit D/A converter
(R-2R type)
UART (SCI)
Extended I/O serial
interface
LCD controller/driver
*1 : As for the necessity of a DIP switch setting (S2) when using the emulation pod (MB2145-507) .
Refer to the hardware manual for the emulation pod (MB2145-507) fomr details.
*2 : Take note of the maximum operating frequency and A/D converter precision restrictions when operating at 3.0 V
to 3.6 V. See the “Electrical Characteristics” section for details.
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