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DM74LS38SJ

Description
Quad 2-Input NAND Buffer with Open-Collector Outputs
Categorylogic    logic   
File Size58KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS38SJ Overview

Quad 2-Input NAND Buffer with Open-Collector Outputs

DM74LS38SJ Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.3
Contacts14
Reach Compliance Codeunknow
seriesLS
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length10.2 mm
Logic integrated circuit typeNAND GATE
MaximumI(ol)0.024 A
Number of functions4
Number of entries2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristicsOPEN-COLLECTOR
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.3
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)12 mA
Prop。Delay @ Nom-Su22 ns
propagation delay (tpd)29 ns
Certification statusNot Qualified
Schmitt triggerNO
Maximum seat height2.1 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width5.3 mm
DM74LS38 Quad 2-Input NAND Buffer with Open-Collector Outputs
August 1986
Revised March 2000
DM74LS38
Quad 2-Input NAND Buffer with Open-Collector Outputs
General Description
This device contains four independent gates, each of which
performs the logic NAND function. The open-collector out-
puts require external pull-up resistors for proper logical
operation.
Pull-Up Resistor Equations
Where:
N
1
(I
OH
)
=
total maximum output high current
for all outputs tied to pull-up resistor
N
2
(I
IH
)
=
total maximum input high current for
all inputs tied to pull-up resistor
N
3
(I
IL
)
=
total maximum input low current for
all inputs tied to pull-up resistor
Ordering Code:
Order Number
DM74LS38M
DM74LS38SJ
DM74LS38N
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Y
=
AB
Inputs
A
L
L
H
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Output
B
L
H
L
H
Y
H
H
H
L
© 2000 Fairchild Semiconductor Corporation
DS006363
www.fairchildsemi.com

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