Freescale Semiconductor, Inc.
MC56F8346/D
Rev. 8.0, 6/2004
56F8346
Preliminary Technical Data
56F8346 16-bit Hybrid Controller
• Up to 60 MIPS at 60MHz core frequency
• DSP and MCU functionality in a unified,
C-efficient architecture
• Access up to 1MB of off-chip program and data
memory
• Chip Select Logic for glueless interface to ROM
and SRAM
• 128KB of Program Flash
• 4KB of Program RAM
• 8KB of Data Flash
• 8KB of Data RAM
• 8KB of Boot Flash
• Two 6-channel PWM Modules
• Four 4-channel, 12-bit ADCs
RSTO
EMI_MODE
EXTBOOT
5
V
PP
2
Freescale Semiconductor, Inc...
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Temperature Sensor
Two Quadrature Decoders
Optional On-Chip Regulator
FlexCAN module
Two Serial Communication Interfaces (SCIs)
Up to two Serial Peripheral Interfaces (SPIs)
Up to four general-purpose Quad Timers
Computer Operating Properly (COP) / Watchdog
JTAG/Enhanced On-Chip Emulation (OnCE™) for
unobtrusive, real-time debugging
• Up to 62 GPIO lines
• 144-pin LQFP Package
V
CAP
4
OCR_DIS
V
DD
V
SS
7
5
Digital Reg
V
DDA
2
V
SSA
RESET
6
3
3
6
3
4
4
4
5
4
4
PWM Outputs
Current Sense Inputs
or GPIOC
Fault Inputs
PWM Outputs
Current Sense Inputs
or GPIOD
Fault Inputs
AD0
AD1
VREF
AD0
AD1
Temp_Sense
PWMA
JTAG/
EOnCE
Port
Analog Reg
16-Bit
56800E Core
Low Voltage
Supervisor
Bit
Manipulation
Unit
PWMB
Program Controller
and
Hardware Looping Unit
Address
Generation Unit
Data ALU
16 x 16 + 36 -> 36-Bit MAC
Three 16-bit Input Registers
Four 36-bit Accumulators
ADCA
PAB
PDB
CDBR
CDBW
Memory
ADCB
Program Memory
64K x 16 Flash
2K x 16 RAM
4K x 16 Boot
Flash
Data Memory
4K x 16 Flash
4K x 16 RAM
XDB2
XAB1
XAB2
PAB
R/W Control
6
External
Address Bus
Switch
2
8
A0-5 or GPIOA8-13
A6-7 or GPIOE2-3
A8-15 or GPIOA0-7
GPIOB0 or A16
4
4
2
2
Quadrature
Decoder 0 or
Quad
Timer A or
GPIOC
Quadrature
Decoder 1 or
Quad
Timer B or
SPI1 or
GPIOC
Quad
Timer C or
GPIOE
Quad
Timer D or
GPIOE
FlexCAN
External Bus
Interface Unit
PDB
CDBR
CDBW
System Bus
Control
External Data
Bus Switch
7
9
D0-6 or GPIOF9-15
D7-15 or GPIOF0-8
WR
RD
IPBus Bridge (IPBB)
Decoding
Peripherals
Clock
resets
Bus Control
2
GPIOD0-1 or CS2-3
PS (CS0) or GPIOD8
Peripheral
Device Selects
RW
Control
IPAB
IPWDB
IPRDB
DS (CS1) or GPIOD9
PLL
SPI0 or
GPIOE
4
SCI1 or
GPIOD
2
SCI0 or
GPIOE
2
COP/
Watchdog
Interrupt
Controller
System
O
Integration
R
Module
CLKO
P
O
Clock
Generator
S
C
XTAL
EXTAL
IRQA IRQB
CLKMODE
56F8346 Block Diagram - 144 LQFP
© Motorola, Inc., 2004. All rights reserved.
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Document Revision History
Version History
Rev 1.0
Rev 2.0
Rev 3.0
Rev 4.0
Description of Change
Pre-Release version, Alpha customers only
Initial Public Release
Corrected typo in
Table 10-4,
Flash Endurance is 10,000 cycles.
Additional grammar issues address
Added Package Pins to GPIO Table in
Part 8, General Purpose Input/Output (GPIO)
Added “Typical Min” values to
Table 10-17
Editing grammar, spelling, consistency of language throughout family
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Updated values in Current Consumption per Power Supply Pin,
Table 10-7,
Regulator Parameters
Table 10-9,
External Clock Operation Timing Requirements
Table 10-13,
SPI Timing
Table 10-18,
ADC Parameters
Table 10-24,
and
IO Loading Coefficients at 10MHz
Table 10-25.
Rev 5.0
Added
Section 4.8,
added the word “access” to FM Error Interrupt in
Table 4-5,
documenting only Typ. numbers for LVI in
Table 10-6,
updated EMI numbers and writeup in
Section 10.9.
Updated numbers in
Table 10-7
and
Table 10-8
with more recent data,
Corrected typo in
Table 10-3
in Pd characteristics.
Replace any reference to Flash Interface Unit with Flash Module, added note to Vcap pin
in
Table 2-2,
corrected thermal numbers for 144 LQFP in
Table 10-3,
removed
unneccessary notes in
Table 10-12;
corrected temperature range in
Table 10-14;
added
ADC calibration information to
Table 10-24
and new graphs in
Figure 10-22.
Corrected EMI pin count in
Figure 1-1,
Clarification to
Table 10-23,
corrected Digital Input
Current Low (pull-up enabled) numbers in
Table 10-5.
Removed text and Table 10-2;
replaced with note to
Table 10-1.
Rev 6.0
Rev 7.0
Rev 8.0
2
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56F8346 Technical Data
Preliminary
Freescale Semiconductor, Inc.
56F8346 Data Sheet Table of Contents
Part 1: Overview . . . . . . . . . . . . . . . . . . . . 4
1.1. 56F8346 Features . . . . . . . . . . . . . . . . . . 4
1.2. 56F8346 Description . . . . . . . . . . . . . . . . 5
1.3. Award-Winning Development
Environment . . . . . . . . . . . . . . . 6
1.4. Architecture Block Diagram . . . . . . . . . . . 7
1.5. Product Documentation . . . . . . . . . . . . . 10
1.6. Data Sheet Conventions . . . . . . . . . . . . 11
Part 8: General Purpose Input/Output
(GPIO) . . . . . . . . . . . . . . . . . . . . . 118
8.1. Introduction . . . . . . . . . . . . . . . . . . . . . 118
8.2. Configuration . . . . . . . . . . . . . . . . . . . . 118
8.3. Memory Maps 122
Part 9: Joint Test Action Group (JTAG) 122
9.1. 56F8346 Information . . . . . . . . . . . . . . 122
Part 2: Signal/Connection Descriptions 12
2.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 12
2.2. 56F8346 Signal Pins . . . . . . . . . . . . . . . 14
Part 10: Specifications . . . . . . . . . . . . . 123
10.1. General Characteristics . . . . . . . . . . . 123
10.2. DC Electrical Characteristics . . . . . . . 127
10.3. Temperature Sense . . . . . . . . . . . . . . 130
10.4. AC Electrical Characteristics . . . . . . . 130
10.5. Flash Memory Characteristics . . . . . . 131
10.6. External Clock Operation Timing . . . . 132
10.7. Phase Locked Loop Timing . . . . . . . . 132
10.8. Crystal Oscillator Timing . . . . . . . . . . 133
10.9. External Memory Interface Timing . . . 133
10.10. Reset, Stop, Wait, Mode Select,
and Interrupt Timing . . . . . . . 136
10.11. Serial Peripheral Interface (SPI)
Timing . . . . . . . . . . . . . . . . . . 138
10.12. Quad Timer Timing . . . . . . . . . . . . . 141
10.13. Quadrature Decoder Timing . . . . . . . 141
10.14. Serial Communication Interface
(SCI) Timing . . . . . . . . . . . . . 142
10.15. Controller Area Network (CAN)
Timing . . . . . . . . . . . . . . . . . . 143
10.16. JTAG Timing . . . . . . . . . . . . . . . . . . 143
10.17. Analog-to-Digital Converter (ADC)
Parameters . . . . . . . . . . . . . . 145
10.18. Equivalent Circuit for ADC Inputs . . . 147
10.19. Power Consumption . . . . . . . . . . . . . 147
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Part 3: On-Chip Clock Synthesis (OCCS) 31
3.1. Introduction . . . . . . . . . . . . . . . . . . . . . . 31
3.2. External Clock Operation . . . . . . . . . . . 32
3.3. Registers . . . . . . . . . . . . . . . . . . . . . . . . 33
Part 4: Memory Map . . . . . . . . . . . . . . . . 34
4.1.
4.2.
4.3.
4.4.
4.5.
4.6.
4.7.
4.8.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Program Map . . . . . . . . . . . . . . . . . . . .
Interrupt Vector Table . . . . . . . . . . . . . .
Data Map . . . . . . . . . . . . . . . . . . . . . . . .
Flash Memory Map . . . . . . . . . . . . . . . .
EOnCE Memory Map . . . . . . . . . . . . . .
Peripheral Memory Mapped Registers .
Factory Programmed Memory . . . . . . . .
34
35
36
39
40
41
41
67
Part 5: Interrupt Controller (ITCN) . . . . . 68
5.1.
5.2.
5.3.
5.4.
5.5.
5.6.
5.7.
Introduction . . . . . . . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . .
Functional Description . . . . . . . . . . . . . .
Block Diagram . . . . . . . . . . . . . . . . . . . .
Operating Modes . . . . . . . . . . . . . . . . . .
Register Descriptions . . . . . . . . . . . . . .
Resets . . . . . . . . . . . . . . . . . . . . . . . . . .
68
68
68
70
70
71
96
Part 11: Packaging . . . . . . . . . . . . . . . . 149
11.1. Package and Pin-Out Information
56F8346 . . . . . . . . . . . . . . . . 149
Part 6: System Integration Module (SIM) 97
6.1.
6.2.
6.3.
6.4.
6.5.
6.6.
6.7.
6.8.
6.9.
Overview . . . . . . . . . . . . . . . . . . . . . . . . 97
Features . . . . . . . . . . . . . . . . . . . . . . . . 97
Operating Modes . . . . . . . . . . . . . . . . . . 98
Operation Mode Register . . . . . . . . . . . 98
Register Descriptions . . . . . . . . . . . . . . 99
Clock Generation Overview . . . . . . . . 112
Power-Down Modes Overview . . . . . . 112
Stop and Wait Mode Disable Function 113
Resets . . . . . . . . . . . . . . . . . . . . . . . . . 113
Part 12: Design Considerations . . . . . . 153
12.1. Thermal Design Considerations . . . . . 153
12.2. Electrical Design Considerations . . . . 154
12.3. Power Distribution and I/O Ring
Implementation . . . . . . . . . . . 155
Part 13: Ordering Information . . . . . . . 156
Part 7: Security Features . . . . . . . . . . . 114
7.1. Operation with Security Enabled . . . . . 114
7.2. Flash Access Blocking Mechanisms . . 114
Please see http://www.motorola.com/semiconductors for the most current Data Sheet revision.
56F8346 Technical Data
Preliminary
3
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Part 1 Overview
1.1 56F8346 Features
1.1.1
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Digital Signal Processing Core
Efficient 16-bit 56800E family hybrid controller engine with dual Harvard architecture
As many as 60 Million Instructions Per Second (MIPS) at 60MHz core frequency
Single-cycle 16
×
16-bit parallel Multiplier-Accumulator (MAC)
Four 36-bit accumulators, including extension bits
Arithmetic and logic multi-bit shifter
Parallel instruction set with unique DSP addressing modes
Hardware DO and REP loops
Three internal address buses
Four internal data buses
Instruction set supports both DSP and controller functions
Controller-style addressing modes and instructions for compact code
Efficient C compiler and local variable support
Software subroutine and interrupt stack with depth limited only by memory
JTAG/EOnCE debug programming interface
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1.1.2
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Memory
Harvard architecture permits as many as three simultaneous accesses to program and data memory
Flash security protection feature
On-chip memory, including a low-cost, high-volume Flash solution
— 128KB of Program Flash
— 4KB of Program RAM
— 8KB of Data Flash
— 8KB of Data RAM
— 8KB of Boot Flash
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Off-chip memory expansion capabilities programmable for 0 - 30 wait states
— Access up to 1MB of program memory or 1MB of data memory
— Chip select logic for glueless interface to ROM and SRAM
EEPROM emulation capability
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1.1.3
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Peripheral Circuits for 56F8346
Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and
three Fault inputs; fault-tolerant design with dead time insertion; supports both center-aligned and
edge-aligned modes
Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions
with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized through Timer
C, channels 2 and 3
Two four-input Quadrature Decoders or two additional Quad Timers
56F8346 Technical Data
Preliminary
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56F8346 Description
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Freescale Semiconductor, Inc...
Temperature Sensor diode can be connected, on the board, to any of the ADC inputs to monitor the
on-chip temperature
Four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C with one pin
and Timer D with two pins
Optional On-Chip Regulator
FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive
Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)
Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional
GPIO lines); SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B
Computer Operating Properly (COP)/Watchdog timer
Two dedicated external interrupt pins
62 General Purpose I/O (GPIO) pins
External reset input pin for hardware reset
External reset output pin for system reset
Integrated low-voltage interrupt module
JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,
real-time debugging
Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock
1.1.4
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Energy Information
Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs
On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be
disabled
On-chip regulators for digital and analog circuitry to lower cost and reduce noise
Wait and Stop modes available
ADC smart power management
Each peripheral can be individually disabled to save power
1.2 56F8346 Description
The 56F8346 is a member of the 56800E core-based family of hybrid controllers. It combines, on
a single chip, the processing power of a DSP and the functionality of a microcontroller with a
flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,
configuration flexibility, and compact program code, the 56F8346 is well-suited for many
applications. The 56F8346 includes many peripherals that are especially useful for motion control,
smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,
automotive control, engine management, noise suppression, remote utility metering, industrial
control for power, lighting, and automation applications.
The 56800E core is based on a Harvard-style architecture consisting of three execution units
operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style
programming model and optimized instruction set allow straightforward generation of efficient,
compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to
enable rapid development of optimized control applications.
The 56F8346 supports program execution from either internal or external memories. Two data
operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8346 also
56F8346 Technical Data
Preliminary
5
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