56F8346 datasheet, PDF - EEWORLD Datasheet

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56F8346: Description16-BIT, 120 MHz, OTHER DSP, PQFP144; Categorysemiconductor The embedded processor and controller; File Size1MB，160 Pages; ManufacturerMotorola ( NXP ); Websitehttps://www.nxp.com

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56F8346 Overview

16-BIT, 120 MHz, OTHER DSP, PQFP144

56F8346 Parametric

Parameter Name	Attribute value
Number of functions	1
Number of terminals	144
Maximum operating temperature	105 Cel
Minimum operating temperature	-40 Cel
Maximum supply/operating voltage	3.6 V
Minimum supply/operating voltage	3 V
Rated supply voltage	3.3 V
External data bus width	16
Processing package description	LQFP-144
state	TRANSFERRED
Craftsmanship	CMOS
packaging shape	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes
Terminal form	GULL WING
Terminal spacing	0.5000 mm
Terminal location	QUAD
Packaging Materials	PLASTIC/EPOXY
Temperature level	INDUSTRIAL
Address bus width	16
barrel shifter	Yes
boundary scan	Yes
Maximum FCLK clock frequency	120 MHz
Internal bus architecture	MULTIPLE
low power mode	Yes
Microprocessor type	OTHER DSP
Number of data processing bits	16

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Freescale Semiconductor, Inc.

MC56F8346/D

Rev. 8.0, 6/2004

56F8346

Preliminary Technical Data

56F8346 16-bit Hybrid Controller

• Up to 60 MIPS at 60MHz core frequency

• DSP and MCU functionality in a unified,

C-efficient architecture

• Access up to 1MB of off-chip program and data

memory

• Chip Select Logic for glueless interface to ROM

and SRAM

• 128KB of Program Flash

• 4KB of Program RAM

• 8KB of Data Flash

• 8KB of Data RAM

• 8KB of Boot Flash

• Two 6-channel PWM Modules

• Four 4-channel, 12-bit ADCs

RSTO

EMI_MODE

EXTBOOT

Freescale Semiconductor, Inc...

•

Temperature Sensor

Two Quadrature Decoders

Optional On-Chip Regulator

FlexCAN module

Two Serial Communication Interfaces (SCIs)

Up to two Serial Peripheral Interfaces (SPIs)

Up to four general-purpose Quad Timers

Computer Operating Properly (COP) / Watchdog

JTAG/Enhanced On-Chip Emulation (OnCE™) for

unobtrusive, real-time debugging

• Up to 62 GPIO lines

• 144-pin LQFP Package

CAP

OCR_DIS

Digital Reg

DDA

SSA

RESET

PWM Outputs

Current Sense Inputs

or GPIOC

Fault Inputs

PWM Outputs

Current Sense Inputs

or GPIOD

Fault Inputs

AD0

AD1

VREF

AD0

AD1

Temp_Sense

PWMA

JTAG/

EOnCE

Port

Analog Reg

16-Bit

56800E Core

Low Voltage

Supervisor

Bit

Manipulation

Unit

PWMB

Program Controller

and

Hardware Looping Unit

Address

Generation Unit

Data ALU

16 x 16 + 36 -> 36-Bit MAC

Three 16-bit Input Registers

Four 36-bit Accumulators

ADCA

PAB

PDB

CDBR

CDBW

Memory

ADCB

Program Memory

64K x 16 Flash

2K x 16 RAM

4K x 16 Boot

Flash

Data Memory

4K x 16 Flash

4K x 16 RAM

XDB2

XAB1

XAB2

PAB

R/W Control

External

Address Bus

Switch

A0-5 or GPIOA8-13

A6-7 or GPIOE2-3

A8-15 or GPIOA0-7

GPIOB0 or A16

Quadrature

Decoder 0 or

Quad

Timer A or

GPIOC

Quadrature

Decoder 1 or

Quad

Timer B or

SPI1 or

GPIOC

Quad

Timer C or

GPIOE

Quad

Timer D or

GPIOE

FlexCAN

External Bus

Interface Unit

PDB

CDBR

CDBW

System Bus

Control

External Data

Bus Switch

D0-6 or GPIOF9-15

D7-15 or GPIOF0-8

IPBus Bridge (IPBB)

Decoding

Peripherals

Clock

resets

Bus Control

GPIOD0-1 or CS2-3

PS (CS0) or GPIOD8

Peripheral

Device Selects

Control

IPAB

IPWDB

IPRDB

DS (CS1) or GPIOD9

PLL

SPI0 or

GPIOE

SCI1 or

GPIOD

SCI0 or

GPIOE

COP/

Watchdog

Interrupt

Controller

System

Integration

Module

CLKO

Clock

Generator

XTAL

EXTAL

IRQA IRQB

CLKMODE

56F8346 Block Diagram - 144 LQFP

For More Information On This Product,

Go to: www.freescale.com

Freescale Semiconductor, Inc.

56F8346 Description

•

Freescale Semiconductor, Inc...

Temperature Sensor diode can be connected, on the board, to any of the ADC inputs to monitor the

on-chip temperature

Four dedicated general-purpose Quad Timers totaling three dedicated pins: Timer C with one pin

and Timer D with two pins

Optional On-Chip Regulator

FlexCAN (CAN Version 2.0 B-compliant ) module with 2-pin port for transmit and receive

Two Serial Communication Interfaces (SCIs), each with two pins (or four additional GPIO lines)

Up to two Serial Peripheral Interfaces (SPIs), both with configurable 4-pin port (or eight additional

GPIO lines); SPI1 can also be used as Quadrature Decoder 1 or Quad Timer B

Computer Operating Properly (COP)/Watchdog timer

Two dedicated external interrupt pins

62 General Purpose I/O (GPIO) pins

External reset input pin for hardware reset

External reset output pin for system reset

Integrated low-voltage interrupt module

JTAG/Enhanced On-Chip Emulation (OnCE) for unobtrusive, processor speed-independent,

real-time debugging

Software-programmable, Phase Lock Loop (PLL)-based frequency synthesizer for the core clock

1.1.4

•

Energy Information

Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs

On-board 3.3V down to 2.6V voltage regulator for powering internal logic and memories; can be

disabled

On-chip regulators for digital and analog circuitry to lower cost and reduce noise

Wait and Stop modes available

ADC smart power management

Each peripheral can be individually disabled to save power

1.2 56F8346 Description

The 56F8346 is a member of the 56800E core-based family of hybrid controllers. It combines, on

a single chip, the processing power of a DSP and the functionality of a microcontroller with a

flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost,

configuration flexibility, and compact program code, the 56F8346 is well-suited for many

applications. The 56F8346 includes many peripherals that are especially useful for motion control,

smart appliances, steppers, encoders, tachometers, limit switches, power supply and control,

automotive control, engine management, noise suppression, remote utility metering, industrial

control for power, lighting, and automation applications.

The 56800E core is based on a Harvard-style architecture consisting of three execution units

operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style

programming model and optimized instruction set allow straightforward generation of efficient,

compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to

enable rapid development of optimized control applications.

The 56F8346 supports program execution from either internal or external memories. Two data

operands can be accessed from the on-chip data RAM per instruction cycle. The 56F8346 also

56F8346 Technical Data

Preliminary

For More Information On This Product,

Go to: www.freescale.com

56F8346 Related Products

	56F8346	MC56F8346
Description	16-BIT, 120 MHz, OTHER DSP, PQFP144	16-BIT, 120 MHz, OTHER DSP, PQFP144
Number of functions	1	1
Number of terminals	144	144
Maximum operating temperature	105 Cel	105 Cel
Minimum operating temperature	-40 Cel	-40 Cel
Maximum supply/operating voltage	3.6 V	3.6 V
Minimum supply/operating voltage	3 V	3 V
Rated supply voltage	3.3 V	3.3 V
External data bus width	16	16
Processing package description	LQFP-144	LQFP-144
state	TRANSFERRED	TRANSFERRED
Craftsmanship	CMOS	CMOS
packaging shape	SQUARE	SQUARE
Package Size	FLATPACK, LOW PROFILE, FINE PITCH	FLATPACK, LOW PROFILE, FINE PITCH
surface mount	Yes	Yes
Terminal form	GULL WING	GULL WING
Terminal spacing	0.5000 mm	0.5000 mm
Terminal location	QUAD	QUAD
Packaging Materials	PLASTIC/EPOXY	PLASTIC/EPOXY
Temperature level	INDUSTRIAL	INDUSTRIAL
Address bus width	16	16
barrel shifter	Yes	Yes
boundary scan	Yes	Yes
Maximum FCLK clock frequency	120 MHz	120 MHz
Internal bus architecture	MULTIPLE	MULTIPLE
low power mode	Yes	Yes
Microprocessor type	OTHER DSP	OTHER DSP
Number of data processing bits	16	16

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