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DM74LS74AM

Description
LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
Categorylogic    logic   
File Size61KB,6 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM74LS74AM Overview

LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14

DM74LS74AM Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeSOIC
package instructionSOP, SOP14,.25
Contacts14
Reach Compliance Codeunknow
seriesLS
JESD-30 codeR-PDSO-G14
JESD-609 codee0
length8.65 mm
Logic integrated circuit typeD FLIP-FLOP
Maximum Frequency@Nom-Su20000000 Hz
MaximumI(ol)0.008 A
Number of digits1
Number of functions2
Number of terminals14
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityCOMPLEMENTARY
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP14,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)8 mA
propagation delay (tpd)35 ns
Certification statusNot Qualified
Maximum seat height1.75 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountYES
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typePOSITIVE EDGE
width3.9 mm
minfmax25 MHz
Base Number Matches1
DM74LS74A Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs
August 1986
Revised March 2000
DM74LS74A
Dual Positive-Edge-Triggered D Flip-Flops with
Preset, Clear and Complementary Outputs
General Description
This device contains two independent positive-edge-trig-
gered D flip-flops with complementary outputs. The infor-
mation on the D input is accepted by the flip-flops on the
positive going edge of the clock pulse. The triggering
occurs at a voltage level and is not directly related to the
transition time of the rising edge of the clock. The data on
the D input may be changed while the clock is LOW or
HIGH without affecting the outputs as long as the data
setup and hold times are not violated. A low logic level on
the preset or clear inputs will set or reset the outputs
regardless of the logic levels of the other inputs.
Ordering Code:
Order Number
DM74LS74AM
DM74LS85ASJ
DM74LS74AN
Package Number
M14A
M14D
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Inputs
PR
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
L
D
X
X
X
H
L
X
Q
H
L
H
L
Q
0
Outputs
Q
L
H
L
H
Q
0
H (Note 1) H (Note 1)
H
=
HIGH Logic Level
X
=
Either LOW or HIGH Logic Level
L
=
LOW Logic Level
↑ =
Positive-going Transition
Q
0
=
The output logic level of Q before the indicated input conditions were
established.
Note 1:
This configuration is nonstable; that is, it will not persist when either
the preset and/or clear inputs return to their inactive (HIGH) level.
© 2000 Fairchild Semiconductor Corporation
DS006373
www.fairchildsemi.com

DM74LS74AM Related Products

DM74LS74AM DM74LS74 74LS74 DM74LS74A DM74LS85ASJ DM74LS74AN
Description LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14 LS SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14
series LS LS LS LS LS LS
Number of digits 1 1 1 1 1 1
Number of functions 2 2 2 2 2 2
Number of terminals 14 14 14 14 14 14
Maximum operating temperature 70 °C 70 Cel 70 Cel 70 Cel 70 Cel 70 °C
Minimum operating temperature - 0.0 Cel 0.0 Cel 0.0 Cel 0.0 Cel -
Output polarity COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY COMPLEMENTARY
surface mount YES Yes Yes Yes Yes NO
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING THROUGH-HOLE
Terminal location DUAL DUAL DUAL DUAL DUAL DUAL
Trigger type POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE POSITIVE EDGE
Maximum supply/operating voltage - 5.25 V 5.25 V 5.25 V 5.25 V -
Minimum supply/operating voltage - 4.75 V 4.75 V 4.75 V 4.75 V -
Rated supply voltage - 5 V 5 V 5 V 5 V -
Processing package description - 0.150 INCH, MS-120, SOIC-14 0.150 INCH, MS-120, SOIC-14 0.150 INCH, MS-120, SOIC-14 0.150 INCH, MS-120, SOIC-14 -
state - ACTIVE ACTIVE ACTIVE ACTIVE -
Craftsmanship - TTL TTL TTL TTL -
packaging shape - RECTANGULAR RECTANGULAR RECTANGULAR RECTANGULAR -
Package Size - SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE SMALL OUTLINE -
Terminal spacing - 1.27 mm 1.27 mm 1.27 mm 1.27 mm -
terminal coating - TIN LEAD TIN LEAD TIN LEAD TIN LEAD -
Packaging Materials - PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY -
Logic IC type - D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP D FLIP-FLOP -
propagation delay TPD - 35 ns 35 ns 35 ns 35 ns -
Max-Min frequency - 25 MHz 25 MHz 25 MHz 25 MHz -
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