DM74S280 datasheet, PDF - EEWORLD Datasheet

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DM74S280: Description9-Bit Parity Generator/Checker; File Size61KB，5 Pages; ManufacturerFairchild; Websitehttp://www.fairchildsemi.com/

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DM74S280 Overview

9-Bit Parity Generator/Checker

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DM74S280 9-Bit Parity Generator/Checker

August 1986

Revised May 2000

DM74S280

9-Bit Parity Generator/Checker

General Description

These universal, nine-bit parity generators/checkers utilize

Schottky-clamped TTL high-performance circuitry, and fea-

ture odd/even outputs to facilitate operation of either odd or

even parity applications. The word-length capability is eas-

ily expanded by cascading.

The DM74S280 can be used to upgrade the performance

of most systems utilizing the DM74180 parity generator/

checker. Although the DM74S280 is implemented without

expander inputs, the corresponding function is provided by

the availability of all input at pin 4, and no internal connec-

tion at pin 3. This permits the DM74S280 to be substituted

for the 180 in existing designs to produce an identical func-

tion, even if DM74S280’s are mixed with existing 180’s.

Input buffers are provided so that each input represents

only one normal 74S load, and full fan-out to 10 normal

Series 74S loads is available from each of the outputs at

low logic levels. A fan-out to 20 normal Series 74S loads is

provided at high logic levels, to facilitate connection of

unused inputs to used inputs.

Features

Generates either odd or even parity for nine data lines

Cascadable for N-bits

Can be used to upgrade existing systems using MSI par-

ity circuits

Typical data-to-output delay—14 ns

Ordering Code:

Order Number

DM74S280M

DM74S280N

Package Number

M14A

N14A

Package Description

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagram

Function Table

Number of Inputs

(A Thru I) that are HIGH

0, 2, 4, 6, 8

1, 3, 5, 7, 9

Outputs

∑

Even

∑

Odd

DS006483

www.fairchildsemi.com

DM74S280 Related Products

	DM74S280	DM74S280M	DM74S280N
Description	9-Bit Parity Generator/Checker	9-Bit Parity Generator/Checker	9-Bit Parity Generator/Checker
Is it lead-free?	-	Contains lead	Contains lead
Is it Rohs certified?	-	incompatible	incompatible
Maker	-	Fairchild	Fairchild
Parts packaging code	-	SOIC	DIP
package instruction	-	SOP, SOP14,.25	0.300 INCH, PLASTIC, MS-001, DIP-14
Contacts	-	14	14
Reach Compliance Code	-	unknow	unknow
Other features	-	ODD/EVEN PARITY GENERATOR	ODD/EVEN PARITY GENERATOR
series	-	S	S
JESD-30 code	-	R-PDSO-G14	R-PDIP-T14
JESD-609 code	-	e0	e0
length	-	8.65 mm	19.18 mm
Logic integrated circuit type	-	PARITY GENERATOR/CHECKER	PARITY GENERATOR/CHECKER
Number of digits	-	9	9
Number of functions	-	1	1
Number of terminals	-	14	14
Maximum operating temperature	-	70 °C	70 °C
Output polarity	-	COMPLEMENTARY	COMPLEMENTARY
Package body material	-	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	-	SOP	DIP
Encapsulate equivalent code	-	SOP14,.25	DIP14,.3
Package shape	-	RECTANGULAR	RECTANGULAR
Package form	-	SMALL OUTLINE	IN-LINE
Peak Reflow Temperature (Celsius)	-	NOT SPECIFIED	NOT SPECIFIED
power supply	-	5 V	5 V
propagation delay (tpd)	-	24 ns	24 ns
Certification status	-	Not Qualified	Not Qualified
Maximum seat height	-	1.75 mm	5.08 mm
Maximum supply voltage (Vsup)	-	5.25 V	5.25 V
Minimum supply voltage (Vsup)	-	4.75 V	4.75 V
Nominal supply voltage (Vsup)	-	5 V	5 V
surface mount	-	YES	NO
technology	-	TTL	TTL
Temperature level	-	COMMERCIAL	COMMERCIAL
Terminal surface	-	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)
Terminal form	-	GULL WING	THROUGH-HOLE
Terminal pitch	-	1.27 mm	2.54 mm
Terminal location	-	DUAL	DUAL
Maximum time at peak reflow temperature	-	NOT SPECIFIED	NOT SPECIFIED
width	-	3.9 mm	7.62 mm

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