DM74S280 9-Bit Parity Generator/Checker
August 1986
Revised May 2000
DM74S280
9-Bit Parity Generator/Checker
General Description
These universal, nine-bit parity generators/checkers utilize
Schottky-clamped TTL high-performance circuitry, and fea-
ture odd/even outputs to facilitate operation of either odd or
even parity applications. The word-length capability is eas-
ily expanded by cascading.
The DM74S280 can be used to upgrade the performance
of most systems utilizing the DM74180 parity generator/
checker. Although the DM74S280 is implemented without
expander inputs, the corresponding function is provided by
the availability of all input at pin 4, and no internal connec-
tion at pin 3. This permits the DM74S280 to be substituted
for the 180 in existing designs to produce an identical func-
tion, even if DM74S280’s are mixed with existing 180’s.
Input buffers are provided so that each input represents
only one normal 74S load, and full fan-out to 10 normal
Series 74S loads is available from each of the outputs at
low logic levels. A fan-out to 20 normal Series 74S loads is
provided at high logic levels, to facilitate connection of
unused inputs to used inputs.
Features
s
Generates either odd or even parity for nine data lines
s
Cascadable for N-bits
s
Can be used to upgrade existing systems using MSI par-
ity circuits
s
Typical data-to-output delay—14 ns
Ordering Code:
Order Number
DM74S280M
DM74S280N
Package Number
M14A
N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Function Table
Number of Inputs
(A Thru I) that are HIGH
0, 2, 4, 6, 8
1, 3, 5, 7, 9
H
L
Outputs
∑
Even
∑
Odd
L
H
© 2000 Fairchild Semiconductor Corporation
DS006483
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DM74S280
Logic Diagram
Typical Applications
Three DM74S280’s can be used to implement a 25-line
parity generator/checker. This arrangement will provide
parity in typically 25 ns. (See Figure 1.)
Longer word lengths can be implemented by cascading
DM74S280’s. As shown in Figure 2, parity can be gener-
ated for word lengths up to 81 bits in typically 25 ns.
FIGURE 1. 25-Line Parity/Generator Checker
FIGURE 2. 81-Line Parity/Generator Checker
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2
DM74S280
Absolute Maximum Ratings
(Note 1)
Supply Voltage
Input Voltage
Operating Free Air Temperature Range
Storage Temperature Range
7V
5.5V
0°C to
+70°C
−65°C
to
+150°C
Note 1:
The “Absolute Maximum Ratings” are those values beyond which
the safety of the device cannot be guaranteed. The device should not be
operated at these limits. The parametric values defined in the Electrical
Characteristics tables are not guaranteed at the absolute maximum ratings.
The “Recommended Operating Conditions” table will define the conditions
for actual device operation.
Recommended Operating Conditions
Symbol
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
Supply Voltage
HIGH Level Input Voltage
LOW Level Input Voltage
HIGH Level Output Current
LOW Level Output Current
Free Air Operating Temperature
0
Parameter
Min
4.75
2
0.8
−1
20
70
Nom
5
Max
5.25
Units
V
V
V
mA
mA
°C
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Symbol
V
I
V
OH
V
OL
I
I
I
IH
I
IL
I
OS
I
CC
Parameter
Input Clamp Voltage
HIGH Level
Output Voltage
LOW Level
Output Voltage
Input Current @ Max Input Voltage
HIGH Level Input Current
LOW Level Input Current
Short Circuit Output Current
Supply Current
Conditions
V
CC
=
Min, I
I
=−18
mA
V
CC
=
Min, I
OH
=
Max
V
IL
=
Max, V
IH
=
Min
V
CC
=
Min, I
OL
=Max
V
IH
=
Min, V
IL
=
Max
V
CC
=
Max, V
I
=
5.5V
V
CC
=
Max, V
I
=
2.7V
V
CC
=
Max, V
I
=
0.5V
V
CC
=
Max (Note 3)
V
CC
Max (Note 4)
−40
67
2.7
3.4
0.5
1
50
−2
−100
105
Min
Typ
(Note 2)
Max
−1.2
Units
V
V
V
mA
µA
mA
mA
mA
Note 2:
All typicals are at V
CC
=
5V, T
A
=
25°C.
Note 3:
Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 4:
I
CC
is measured with all inputs grounded and all outputs OPEN.
Switching Characteristics
at V
CC
=
5V and T
A
=
25°C
R
L
=
280Ω
Symbol
Parameter
From (Input)
To (Output)
t
PLH
t
PHL
t
PLH
t
PHL
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Propagation Delay Time
LOW-to-HIGH Level Output
Propagation Delay Time
HIGH-to-LOW Level Output
Data to
∑
Even
Data to
∑
Even
Data to
∑
Odd
Data to
∑
Odd
C
L
=
15 pF
Min
Max
21
18
21
18
R
L
=
280Ω
C
L
=
50 pF
Min
Max
24
21
24
21
ns
ns
ns
ns
Units
3
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DM74S280
Physical Dimensions
inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow
Package Number M14A
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4
DM74S280 9-Bit Parity Generator/Checker
Physical Dimensions
inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
5
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
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