E-STLC5048TR datasheet, PDF - EEWORLD Datasheet

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E-STLC5048TR: DescriptionA/MU-LAW, PROGRAMMABLE CODEC, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64; CategoryWireless rf/communication Telecom circuit; File Size524KB，64 Pages; ManufacturerSTMicroelectronics; Websitehttp://www.st.com/

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E-STLC5048TR Overview

A/MU-LAW, PROGRAMMABLE CODEC, PQFP64, 10 X 10 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-64

E-STLC5048TR Parametric

Parameter Name	Attribute value
Maker	STMicroelectronics
Parts packaging code	QFP
package instruction	LFQFP,
Contacts	64
Reach Compliance Code	unknown
Law of compression and extension	A/MU-LAW
filter	YES
JESD-30 code	S-PQFP-G64
length	10 mm
Number of functions	1
Number of terminals	64
Operating mode	SYNCHRONOUS
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	LFQFP
Package shape	SQUARE
Package form	FLATPACK, LOW PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.6 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	PROGRAMMABLE CODEC
Temperature level	INDUSTRIAL
Terminal form	GULL WING
Terminal pitch	0.5 mm
Terminal location	QUAD
width	10 mm
Base Number Matches	1

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STLC5048

Fully programmable four-channel codec and filter

Features

■

Fully programmable monolithic 4-channel

codec/filter

Single +3.3 V supply

A/m law programmable

Linear coding (16 bits) option

PCM highway format automatically detected:

1.536 or 1.544 MHz, 2.048, 4.096, 8192 MHz

Two PCM ports available

TX gain programming: 33 dB range; <0.01 dB

step

RX gain programming: 42 dB range; <0.01 dB

step

Programmable SLIC input impedance

Programmable transhybrid balance filter

Programmable equalization (frequency

response)

Programmable time slot assignment

Digital and analog loopbacks

SLIC control port static (16 I/Os),

dynamic (12 I/Os + 4 CS)

TQFP64 (10x10x1.4mm)

Description

The STLC5048 is a monolithic fully programmable

4-channel codec and filter. It operates with a

single +3.3V supply.

The analog interface is based on a receive output

buffer driving the SLIC RX input and on an

amplifier input stage normally driven by the SLIC

TX output. Due to the single supply voltage a mid-

supply reference level is generated internally by

the device and all analog signals are referred to

this level (AGND). The PCM interface uses one

common 8 kHz frame sync. pulse for transmit and

receive direction. The bit clock is automatically

detected between four standards:

1.563/1.544 MHz, 2.048 MHz, 4.096 MHz,

8192 MHz.

Built-in test mode with tone generation, MCU

access to PCM data

64 TQFP (10x10mm) package

Programmable SLIC line current limitation

Programmable SLIC off-hook detection

threshold

-O

Two PCM port are provided: the channels can be

connected to port A or/and B.

Device programmability is achieved by means of

several registers and commands allowing to set

the different parameters like TX/RX gains, line

impedance, transhybrid balance, equalization

(frequency response), encoding law (A/m), time

slot assignment, independent channels power

up/down, loopbacks, PCM bits offset.

The STLC5048 can be programmed via serial

interface running up to 8 MHz. One interrupt

output pin is also provided.

A GUI interface is also available to emulate and

program the coefficients for impedance synthesis,

echo cancelling and channel filtering.

November 2007

Rev 9

1/64

www.st.com

Contents

STLC5048

Contents

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Absolute maximum ratings and operating conditions . . . . . . . . . . . . . 9

Pin assignments and descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

4.9

4.10

4.11

4.12

4.13

Power on initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Power down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Ringing state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Impedance synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Echo canceling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Transmit path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Receive path . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

PCM interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

MCU control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Programming the device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

SLIC control interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC SLIC programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Built-in test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.1

I/O direction register (DIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I/O data register channel #0 (DATA0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

I/O data register channel #1 (DATA1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

I/O data register channel #2 (DATA2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

I/O data register channel #3 (data3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Persistency check register (PCHK-A/B) . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Interrupt register (INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interrupt mask register for I/O port (DMASK) . . . . . . . . . . . . . . . . . . . . . . 28

Interrupt mask register for interrupt (IMASK) . . . . . . . . . . . . . . . . . . . . . . 28

Alarm register (ALARM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5.2

5.3

5.4

5.5

5.6

5.7

5.8

5.9

5.10

-O

2/64

STLC5048

Contents

5.11

5.12

5.13

5.14

5.15

5.16

5.17

5.18

5.19

5.20

5.21

5.22

5.23

5.24

5.25

5.26

5.27

5.28

5.29

5.30

5.31

5.32

5.33

5.34

Configuration register (CONF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Command enable register (COMEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Synchronous check register (SYNCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DSP status register (CTRLACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Checksum register (CKSUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Loopback register (LOOPB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Transmit pre-amplifier gain register (TXG) . . . . . . . . . . . . . . . . . . . . . . . . 32

Receive amplifier gain register (RXG) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SLIC line current limit reg (ILIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SLIC off-hook threshold register (ITH) . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PCM shift register (PCMSH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PCM command register (PCMCOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Transmit time slot ch #0 (DXTS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Transmit time slot ch #1 (DXTS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Transmit time slot ch #2 (DXTS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Transmit time slot ch #3 (DXTS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Receive time slot ch #0 (DRTS0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Receive time slot ch #1 (DRTS1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Receive time slot ch #2 (DRTS2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Receive time slot ch #3 (DRTS3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

PCMW data register (PCMWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

PCMR data register (PCMRD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

PCM control register (PCMCTRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Tone generation register (TONEG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Coefficient state register (COEFST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Software revision ID Code (SWRID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

Hardware revision ID code (HWRID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

5.36

5.37

6.1

6.2

5.35

-O

Single byte instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Realignment command (REACOM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Start checksum calculation (CKSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . 44

Command list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3/64

Contents

STLC5048

Command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

8.1

8.2

8.3

8.4

8.5

8.6

8.7

8.8

8.9

8.10

Block enable command (BLKEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

KD filter (KDF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

AFE coefficient (AFE_CFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Timeout value (T_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Receive gain (GRX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Transmit gain (GTX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

R filter coefficient (RFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

X filter coefficient (XFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

B filter coefficient (BFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Z filter coefficient (ZFC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50

Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

Appendix A Absolute gains in kit with L3235N/STLC3080 . . . . . . . . . . . . . . . . . 58

Appendix B STLC5048 application diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

Appendix C Power sequences. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

C.1

C.2

Power-up sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Power-on sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

-O

4/64

STLC5048

List of tables

Table 1.

Table 2.

Table 3.

Table 4.

Table 5.

Table 6.

Table 7.

Table 8.

Table 9.

Table 10.

Table 11.

Table 12.

Table 13.

Table 14.

Table 15.

Table 16.

Table 17.

Table 18.

Table 19.

Table 20.

Table 21.

Table 22.

Table 23.

Table 24.

Table 25.

Table 26.

Table 27.

Table 28.

Table 29.

Table 30.

Table 31.

Table 32.

Table 33.

Table 34.

Table 35.

Table 36.

Table 37.

Table 38.

Table 39.

Table 40.

Table 41.

Table 42.

Table 43.

Table 44.

Table 45.

Table 46.

Table 47.

Table 48.

Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

I/O definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Instruction byte structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

I/O direction register (DIR) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Dynamic I/O data register channel #0 (DATA0) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Static I/O data register channel #0 (DATA0) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Dynamic I/O data register channel #1 (DATA1) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Static I/O data register channel #1 (DATA1) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Dynamic I/O data register channel #2 (DATA2) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Static I/O data register channel #2 (DATA2) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Dynamic I/O data register channel #3 (data3) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Dynamic I/O data register channel #3 (data3) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

A and B inputs of persistency check register in static mode. . . . . . . . . . . . . . . . . . . . . . . . 26

Persistency check register (PCHK-A/B) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Interrupt register (INT) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Interrupt mask register for I/O port (DMASK) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Interrupt mask register for interrupt (IMASK) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Alarm register (ALARM) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Configuration register (CONF) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Command enable register (COMEN) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Synchronous check register (SYNCK) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

DSP status register (CTRLACK) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Checksum register (CKSUM) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Loopback register (LOOPB) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Transmit pre-amplifier gain register (TXG) bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Receive amplifier gain register (RXG) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SLIC line current limit reg (ILIM) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

SLIC off-hook threshold register (ITH) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PCM shift register (PCMSH) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PCM command register (PCMCOM) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

PCM command register (PCMCOM) TPB and TPA bit combinations . . . . . . . . . . . . . . . . 35

PCM command register (PCMCOM) PC0 and PC1 bit combinations . . . . . . . . . . . . . . . . 35

Transmit time slot ch #0 (DXTS0) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Transmit time slot ch #0 (DXTS0) time slots in linear mode . . . . . . . . . . . . . . . . . . . . . . . . 36

Transmit time slot ch #1 (DXTS1) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Transmit time slot ch #1 (DXTS1) time slots in linear mode . . . . . . . . . . . . . . . . . . . . . . . . 37

-O

5/64

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