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DM81LS97AN

Description
3-STATE Octal Buffer
Categorylogic    logic   
File Size73KB,7 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM81LS97AN Overview

3-STATE Octal Buffer

DM81LS97AN Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instruction0.300 INCH, MS-001, PLASTIC, DIP-20
Contacts20
Reach Compliance Codeunknow
Is SamacsysN
Control typeENABLE LOW
seriesLS
JESD-30 codeR-PDIP-T20
JESD-609 codee0
length26.075 mm
Logic integrated circuit typeBUS DRIVER
MaximumI(ol)0.012 A
Number of digits8
Number of functions1
Number of ports2
Number of terminals20
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP20,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)26 mA
Prop。Delay @ Nom-Su28 ns
propagation delay (tpd)40 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
width7.62 mm
Base Number Matches1
DM81LS95A • DM81LS96A • DM81LS97A 3-STATE Octal Buffer
September 1991
Revised May 1999
DM81LS95A • DM81LS96A • DM81LS97A
3-STATE Octal Buffer
General Description
These devices provide eight, two-input buffers in each
package. All employ low-power-Schottky TTL technology.
One of the two inputs to each buffer is used as a control
line to gate the output into the high-impedance state, while
the other input passes the data through the buffer. The
DM81LS95A and DM81LS97A present true data at the out-
puts, while the DM81LS96A is inverting. On the
DM81LS95A and DM81LS96A versions, all eight 3-STATE
enable lines are common, with access through a 2-input
NOR gate. On the DM81LS97A version, four buffers are
enabled from one common line, and the other four buffers
are enabled form another common line. In all cases the
outputs are placed in the 3-STATE condition by applying a
high logic level to the enable pins.
Features
s
Typical power dissipation
DM81LS95A, DM81LS97A
DM81LS96A
s
Typical propagation delay
DM81LS95A, DM81LS97A
DM81LS96A
15 ns
10 ns
80 mW
65 mW
s
Low power-Schottky, 3-STATE technology
Ordering Code:
Order Number
DM81LS95AWM
DM81LS95AN
DM81LS96AWM
DM81LS96AN
DM81LS97AN
Package Number
M20B
N20A
M20B
N20A
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
DM81LS95A and DM92LS96A
Pin Names
A1–A8
Y1–Y8
G1–G2
Inputs
Outputs
Active LOW Output Enables (Note 1)
Descriptions
Note 1:
Both G1 and G2 must be LOW for outputs to be enabled.
DM81LS97A
Pin Names
A1–A8
Y1–Y8
G1
G2
Inputs
Outputs
Active LOW Output Enable (Y1–Y4)
Active LOW Output Enable (Y5–Y8)
Descriptions
© 1999 Fairchild Semiconductor Corporation
DS006435
www.fairchildsemi.com

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