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DM9334N

Description
8-Bit Addressable Latch
Categorylogic    logic   
File Size59KB,5 Pages
ManufacturerFairchild
Websitehttp://www.fairchildsemi.com/
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DM9334N Overview

8-Bit Addressable Latch

DM9334N Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerFairchild
Parts packaging codeDIP
package instructionDIP, DIP16,.3
Contacts16
Reach Compliance Codeunknow
Other features1:8 DMUX FOLLOWED BY LATCH
series93
JESD-30 codeR-PDIP-T16
JESD-609 codee0
length19.305 mm
Logic integrated circuit typeD LATCH
MaximumI(ol)0.016 A
Number of digits1
Number of functions1
Number of terminals16
Maximum operating temperature70 °C
Minimum operating temperature
Output polarityTRUE
Package body materialPLASTIC/EPOXY
encapsulated codeDIP
Encapsulate equivalent codeDIP16,.3
Package shapeRECTANGULAR
Package formIN-LINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
power supply5 V
Maximum supply current (ICC)86 mA
Prop。Delay @ Nom-Su35 ns
propagation delay (tpd)35 ns
Certification statusNot Qualified
Maximum seat height5.08 mm
Maximum supply voltage (Vsup)5.25 V
Minimum supply voltage (Vsup)4.75 V
Nominal supply voltage (Vsup)5 V
surface mountNO
technologyTTL
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal pitch2.54 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
Trigger typeLOW LEVEL
width7.62 mm
DM9334 8-Bit Addressable Latch
August 1986
Revised February 2000
DM9334
8-Bit Addressable Latch
General Description
The DM9334 is a high speed 8-bit Addressable Latch
designed for general purpose storage applications in digital
systems. It is a multifunctional device capable of storing
single line data in eight addressable latches, and being a
one-of-eight decoder and demultiplexer with active level
HIGH outputs. The device also incorporates an active level
LOW common clear for resetting all latches, as well as an
active level LOW enable.
The DM9334 has four modes of operation which are shown
in the mode selection table. In the addressable latch mode,
data on the data line (D) is written into the addressed latch.
The addressed latch will follow the data input with all non-
addressed latches remaining in their previous states. In the
memory mode, all latches remain in their previous state
and are unaffected by the data or address inputs.
In the one-of-eight decoding or demultiplexing mode, the
addressed output will follow the state of the D input with all
other inputs in the LOW state. In the clear mode all outputs
are LOW and unaffected by the address and data inputs.
When operating the device as an addressable latch,
changing more than one bit of the address could impose a
transient wrong address. Therefore, this should only be
done while in the memory mode.
The function tables summarize the operation of the prod-
uct.
Features
s
Common clear
s
Easily expandable
s
Random (addressable) data entry
s
Serial to parallel capability
s
8 bits of storage/output of each bit available
s
Active high demultiplexing/decoding capability
Ordering Code:
Order Number
DM9334N
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
© 2000 Fairchild Semiconductor Corporation
DS006609
www.fairchildsemi.com

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