Advance Data Sheet
March 2000
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Features
Quad 10 Mbits/s Transceiver
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Quad 100 Mbits/s FX Transceiver
s
Compatible with
IEEE
802.3u 100Base-FX stan-
dard.
Reuses existing twisted-pair I/O pins for compatible
fiber-optic transceiver pseudo-ECL (PECL) data.
Fiber mode automatically configures port:
— FX mode enable is pin or register selectable
— Disables autonegotiation and 10Base-T.
— Enables 100Base-FX remote fault signaling.
— Disables MLT-3 encoder/decoder.
— Disables scrambler/descrambler.
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DSP based.
Compatible with
IEEE
* 802.3 10Base-T standard
for twisted-pair cable.
Half- and full-duplex operations.
Autopolarity detection and correction.
Adjustable squelch level for extended wire-length
capability (two levels).
Interfaces with
IEEE
802.3u media independent
interface (MII) or a serial 10 Mbits/s 7-pin interface.
On-chip filtering eliminates the need for external fil-
ters.
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General
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Ports individually configurable
Autonegotiation and management:
— Fast link pulse (FLP) burst generator.
— Arbitration function.
— Accepts preamble suppression.
— Operates up to 12.5 MHz.
Supports the MII station management protocol and
frame format (clause 22): basic and extended reg-
ister set.
Supports next page.
Provides status signals: receive activity, transmit
activity, full duplex, collision/jabber, link integrity,
and speed indication.
Powerdown mode for 10 Mbits/s and 100 Mbits/s
operation.
Loopback testing for 10 Mbits/s and 100 Mbits/s
operation.
0.25
µm
low-power CMOS technology.
Single 3.3 V power supply operation.
25 MHz XTAL oscillator input or 25 MHz/50 MHz/
125 MHz clock input.
Compatible with RMII (standard version) and SMII
(standard version).
Quad 100 Mbits/s Transceiver
s
Compatible with
IEEE
802.3u MII (clause 22),
PCS/PMA (clause 24), PMD (clause 25), MII man-
agement, and autonegotiation (clause 28) specifi-
cations.
Selectable 5-bit code-group (PDT/PDR interface)
or 4-bit data nibbles (MII interface) I/O.
Full- or half-duplex operations.
Optional carrier integrity monitor (CIM).
Selectable carrier sense signal generation (MCRS)
asserted during either transmission or reception in
half duplex (MCRS asserted during reception only
in full duplex).
Adaptive equalization and baseline wander correc-
tion.
On-chip filtering eliminates the need for external
filters.
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*
IEEE
is a registered trademark of The Institute of Electrical and
Electronics Engineers, Inc.
s
Note: Advisories are issued as needed to update product information. When using this data sheet for design purposes, please contact
your Lucent Technologies Microelectronics Group Account Manager to obtain the latest advisory on this product.
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Table of Contents
Contents
Page
Features .................................................................................................................................................................... 1
Quad 10 Mbits/s Transceiver .......................................................................................................................................................1
Quad 100 Mbits/s Transceiver .....................................................................................................................................................1
Quad 100 Mbits/s FX Transceiver ...............................................................................................................................................1
General........................................................................................................................................................................................1
Description ................................................................................................................................................................ 4
Functional Block Diagram ...........................................................................................................................................................4
Macrocell I/Os .............................................................................................................................................................................5
Signal Information...................................................................................................................................................... 6
Signal Descriptions .....................................................................................................................................................................6
MII Station Management .........................................................................................................................................13
Basic Operation.........................................................................................................................................................................13
MII Interface Design ................................................................................................................................................14
Absolute Maximum Ratings.....................................................................................................................................14
Electrical Characteristics .........................................................................................................................................15
Register Information ................................................................................................................................................19
Register Descriptions ................................................................................................................................................................19
Application Notes: Board Layout .............................................................................................................................31
Board Layout Considerations ....................................................................................................................................................31
Tables
Page
Table 1. MII/5-Bit Serial Interface Signals................................................................................................................. 6
Table 2. MII Management Signals ............................................................................................................................ 7
Table 3. 10/100 Mbits/s Twisted-Pair (TP) Interface Signals..................................................................................... 7
Table 4. Status Signals .............................................................................................................................................8
Table 5. Clock and Reset Signals ............................................................................................................................. 9
Table 6. Control/Status Signals ..............................................................................................................................10
Table 7. Testability Signals......................................................................................................................................12
Table 8. MII Management Frame Format................................................................................................................13
Table 9. MII Management Frames—Field Description............................................................................................13
Table 10 . Absolute Maximum Ratings ...................................................................................................................14
Table 11 . Operating Conditions .............................................................................................................................14
Table 12. Summary of Management Registers (MR) .............................................................................................19
Table 13. MR0—Control Register Bit Descriptions .................................................................................................20
Table 14. MR1—Status Register Bit Descriptions ..................................................................................................21
Table 15. MR2, MR3—PHY Identification Registers (1 and 2) Bit Descriptions .....................................................22
Table 16. MR4—Autonegotiation Advertisement Register Bit Descriptions............................................................22
Table 17. MR5—Autonegotiation Link Partner Ability (Base Page) Register Bit Descriptions................................23
Table 18. MR5—Autonegotiation Link Partner (LP) Ability Register (Next Page) Bit Descriptions .........................23
Table 19. MR6—Autonegotiation Expansion Register Bit Descriptions..................................................................24
Table 20. MR7—Next Page Transmit Register Bit Descriptions..............................................................................25
Table 21. MR16—PCS Control Register Bit Descriptions.......................................................................................25
Table 22. MR17—Autonegotiation Read Register A...............................................................................................26
Table 23. MR18—Autonegotiation Read Register B...............................................................................................26
Table 24. MR20—User-Defined Register ...............................................................................................................27
Table 25. MR21—RXER Counter ...........................................................................................................................27
Table 26. MR28—Device-Specific Register 1 (Status Register) Bit Descriptions ...................................................27
2
Advance Data Sheet
March 2000
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Table of Contents
(continued)
Tables
(continued)
Page
Table 27. MR29—Device-Specific Register 2 (100 Mbits/s Control) Bit Descriptions.............................................28
Table 28. MR30—Device-Specific Register 3 (10 Mbits/s Control) Bit Descriptions...............................................29
Table 29. MR31—Device-Specific Register 4 (Quick Status) Bit Descriptions .......................................................30
Figures
Page
Figure 1. DNC3X3425 Functional Block Diagram ....................................................................................................4
Figure 2. I/Os of the DNC3X3425 Macrocell ............................................................................................................5
Figure 3. DNC MII TX Logic ...................................................................................................................................15
Figure 4. DNC MII RX Logic ...................................................................................................................................15
Figure 5. DNC Maintenance Logic .........................................................................................................................15
Figure 6. Typical Application (One Channel Shown) ..............................................................................................16
Figure 7. Pinout Assignment ..................................................................................................................................17
Figure 8. Typical Single-Channel Twisted-Pair (TP) Interface.................................................................................18
3
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Advance Data Sheet
March 2000
Description
The DNC3X3425 is a twisted-pair transceiver macrocell that supports transmission and reception over category 3
unshielded twisted-pair (UTP) cable and category 5 UTP
.
The DNC3X3425 has been designed specifically for applications that support both 10Base-T and 100Base-X, such
as network interface cards (NICs) and switches.
Figure 1 represents a functional block diagram of the DNC3X3425 macrocell.
Figure 2 shows the I/Os of the DNC3X3425 macrocell.
4
Functional Block Diagram
100 Mbits/s TRANSCEIVER
MTXD[3:0]
PDT
SCRAMBLER
PMD
TX
4B/5B
ENCODER
FAR-END
FAULT GEN.
MCRS
MCOL
MRXD[3:0]
MRX_DV
MRX_ER
MRXCLK
MTXCLK
MTXD[3:0]
MTX_EN
MTX_ER
TX STATE
MACHINE
SD
COLLISION
SD
DETECT
RX STATE
MACHINE
SD
TPO±
MII
INTERFACE
MII
CAR_STAT
CIM
RXERR_ST
CARRIER
DETECT
ALIGNER
DESCRAMBLER
PDR/
DCRU
SD
PMD
RX
5B/4B
DECODER
FAR-END
FAULT DETECT
TPI±
SERIAL/PARALLEL
INTERFACE
CLK20
LC10 LS10
MANAGEMENT
INTERFACE
MDC
MDIO
10 Mbits/s TRANSCEIVER
LC100
LS100
MII
MANAGEMENT
25 MHz
AUTONEGOTIATION
AND LINK MONITOR
RMCLK
125 MH
Z
FREQ.
SYNTH.
125 MHz
20 MHz
25 MHz
CRYSTAL
5-5136(F).j
Figure 1. DNC3X3425 Functional Block Diagram (1 Channel Shown)
4
Advance Data Sheet
March 2000
DNC3X3425
Quad 10/100 Mbits/s Ethernet Transceiver Macrocell
Description
(continued)
Macrocell I/Os
ATBON
APFE_PIN[3:0]
ATBOP
AUTO_EN[3:0]
AUTODONE[3:0]
BYPPD125
CK125P
BYPPD160
CK160
CARIN_IN[3:0]
CLK25RAW
CK125_BUF
CS[3:0]
CRS_SEL[3:0]
ECLN
EDBT[3:0]
ECLP
ELLE_PIN[3:0]
FDUP_OUT[3:0]
EN_RMCK
INT_R31[3:0]
EN_XTL
LS100_OK[3:0]
FASTSEL[1:0]
LS10_OK[3:0]
FASTTEST
LS_OK[3:0]
FX_MODE[3:0]
MCOL[3:0]
F_DUP[3:0]
MCRS[3:0]
HBT_PIN[3:0]
MDIO_HI_Z
HWRESET
MDIO_OUT
IN125
MRXCLK[3:0]
INT_MASK[3:0]
MRXD[3:0][3:0]
ISOLATE[3:0]
MRX_DV[3:0]
LED_STR_EN
MRX_ER[3:0]
LED_BLINK_EN
MTXCLK[3:0]
LITF_ENH
RG20_OUT[15:0][3:0]
LPBK_PIN[3:0]
REXT10
MDC
REXT100
MDIO_IN
REXTBS
MGT_ADD[4:2]
RMCLKRAW
MODEL[3:0]
RS[3:0]
MTXD[3:0][3:0]
RST_10_BUSY[3:0]
MTX_EN[3:0]
RST_BUSY[3:0]
MTX_ER[3:0]
RST_TX_BUSY[3:0]
NOLP_PIN[3:0]
SERIAL_SEL[3:0]
OUI[24:3]
SLOWCLK[3:0]
POR
TESTCOL[3:0]
PWRDN[3:0]
TESTCRS[3:0]
RMCLK
TESTMDHZ
SDBT[3:0]
TESTMDOUT
SDFX[3:0]
TESTRXCK[3:0]
SECUR[3:0]
TESTRXDV[3:0]
SER_SEL_PIN[3:0]
TESTRXD[3:0][3:0]]
SPEED_PIN[3:0]
TESTRXER[3:0]
TESTMDC
TESTMDIN
TESTTXCK[3:0]
TESTSEL[3:0]
TPAPS[3:0]
TESTTXD[3:0]
TPJS[3:0]
TESTTXEN
TPO[3:0]
TESTTXER
TPOB[3:0]
TPI[3:0]
XHI
TPIB[3:0]
XS[3:0]
VERSION[3:0]
XLO
4
DNC3X3425
5-7541(F).a.r2
Figure 2. I/Os of the DNC3X3425 Macrocell
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