DATASHEET
ISL8120
Dual/n-Phase Buck PWM Controller with Integrated Drivers
The
ISL8120
integrates two voltage-mode PWM leading-edge
modulation control, with input feed-forward synchronous buck
PWM controllers, to control a dual independent voltage
regulator or a 2-phase single output regulator. It also
integrates current sharing control for the power module to
operate in parallel, which offers high system flexibility.
The ISL8120 integrates an internal linear regulator, which
generates VCC from input rail for applications with only one
single supply rail. The internal oscillator is adjustable from
150kHz to 1.5MHz, and is able to synchronize to an external
clock signal for frequency synchronization and phase paralleling
applications. Its PLL circuit can output a phase-shift
programmable clock signal for the system to be expanded to 3-,
4-, 6-, 12- phases with desired interleaving phase shift.
The ISL8120’s Fault Hand Shake feature protects any channel
from overloading/stressing due to system faults or phase
failure. The undervoltage fault protection features are also
designed to prevent a negative transient on the output voltage
during falling down. This eliminates the Schottky diode that is
used in some systems for protecting the load device from
reversed output voltage damage.
FN6641
Rev.3.00
July 20, 2016
Features
• Wide V
IN
range operation: 3V to 22V
- V
CC
operation from 3V to 5.60V
• Excellent output voltage regulation: 0.6V ±0.6%/±0.9%
internal reference over commercial/industrial temperature
• Frequency synchronization
• Programmable phase shift for 1-, 2-, 3-, 4-, 6-, up to
12-phase applications
• Fault hand shake capability for high system reliability
• Digital soft-start with precharged output start-up capability
• Dual independent channel enable inputs with precision
voltage monitor and voltage feed-forward capability
- Programmable input voltage POR and its hysteresis with a
resistor divider at EN input
• Extensive circuit protection functions: output overvoltage,
undervoltage, overcurrent protection, over temperature and
pre-power-on reset overvoltage protection option
Related Literature
• Technical Brief
TB389
“PCB Land Pattern Design and Surface
Mount Guidelines for QFN (MLFP) Packages”
•
AN1528,
“ISL8120EVAL3Z Evaluation Board Setup
Procedure”
•
AN1607,
“ISL8120EVAL4Z Evaluation Board Setup
Procedure”
Applications
• Power supply for datacom/telecom and POL
• Paralleling power module
• Wide and narrow input voltage range buck regulators
• DDR I and II applications
• High current density power supplies
• Multiple outputs VRM and VRD
CHANNELS 1 AND 2 GATE DRIVE
PVCC
3Ω
BOOTn
UGATEn
PWMn
10kΩ
FAULT LOGIC
GATE
CONTROL
LOGIC
SHOOT-
THROUGH
PROTECTION
10kΩ
LGATEn
PHASEn
FIGURE 1. INTEGRATED DRIVER BLOCK DIAGRAM
FN6641 Rev.3.00
July 20, 2016
Page 1 of 39
ISL8120
Table of Contents
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2-Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
2-Phase Operation with r
DS(ON)
Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Dual Regulators with DCR Sensing and Remote Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
Double Data Rate I or II . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3-Phase Regulator with Precision Resistor Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4-Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Multiple Power Modules in Parallel with Current Sharing Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3-Phase Regulator with Resistor Sensing and 1 Phase Regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6-Phase Operation with DCR Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Typical Performance Curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Modes of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage Feed-Forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power-Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overvoltage and Undervoltage Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PRE-POR Overvoltage Protection (PRE-POR-OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Over-Temperature Protection (OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Inductor Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Resistive Sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Overcurrent Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sharing Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Series Linear and Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Frequency Synchronization and Phase Lock Loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Amplifier for Remote Sense . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal Reference and System Accuracy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DDR and Dual Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Layout Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
23
24
24
25
25
25
26
26
26
27
28
29
32
33
33
33
34
35
36
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
FN6641 Rev.3.00
July 20, 2016
Page 2 of 39
ISL8120
Pin Configuration
ISL8120
(32 LD QFN)
TOP VIEW
VSEN1+
ISEN1B
ISEN1A
VSEN1-
VMON1
BOOT1
25
24 UGATE1
23 PHASE1
22 LGATE1
33
GND
21 PVCC
20 LGATE2
19 PHASE2
18 UGATE2
17 BOOT2
9
COMP2
10
FB2
11
VMON2
12
VSEN2-
13
VSEN2+
14
ISEN2B
15
ISEN2A
16
VIN
32
COMP1 1
ISET 2
ISHARE 3
EN/VFF1 4
FSYNC 5
EN/VFF2 6
CLKOUT/REFIN 7
PGOOD 8
31
30
29
28
27
Functional Pin Descriptions
PIN
NUMBER
1
9
SYMBOL
COMP1
COMP2
DESCRIPTION
These pins are the error amplifier outputs. They should be connected to FB1, FB2 pins through desired compensation
networks when both channels are operating independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the
corresponding error amplifier is disabled and its output (COMP pin) is high impedance. Thus, in multiphase operations,
all other SLAVE phases’ COMP pins can tie to the MASTER phase’s COMP1 pin (1st phase), which modulates each
phase’s PWM pulse with a single voltage feedback loop. While the error amplifier is not disabled, an independent
compensation network is required for each cascaded IC.
This pin sources a 15µA offset current plus the average current of both channels in multiphase mode or only Channel
1’s current in independent mode. The voltage (VISET) set by an external resistor (RISET) represents the average current
level of the local active channel(s).
This pin is used for current sharing purposes and is configured to current share bus representing all modules’ average
current. It sources 15µA offset current plus the average current of both channels in multiphase mode or Channel 1’s
current in independent mode. The share bus (ISHARE pins connected together) voltage (VISHARE) set by an external
resistor (RISHARE) represents the average current level of all ISL8120 controller connected to current share bus. The
ISHARE bus voltage compares with ISET voltage to generates current share error signal for current correction block of
each cascaded controller. The share bus impedance RISHARE should be set as RISET/NCTRL (RISET divided by number
of ISL8120 in current sharing controllers). There is a 1.2V threshold for average overcurrent protection on this pin.
VISHARE is compared with a 1.2V threshold for average overcurrent protections. For full-scale current, RISHARE should
be 1.2V/123µA = ~10kΩ. Typically 10kΩ is used for RSHARE and RSET.
These pins have triple functions. The voltage on EN/FF_ pin is compared with a precision 0.8V threshold for system
enable to initiate soft-start. With a voltage lower than the threshold, the corresponding channel can be disabled
independently. By connecting these pins to the input rail through a voltage resistor divider, the input voltage can be
monitored for UVLO (Undervoltage Lockout) function. The undervoltage lockout and its hysteresis levels can be
programmed by these resistor dividers. The voltages on these pins are also fed into the controller to adjust the sawtooth
amplitude of each channel independently to realize the feed-forward function.
Furthermore, during fault (such as overvoltage, overcurrent, and over-temperature) conditions, these pins are pulled low
to communicate the information to other cascaded ICs.
2
ISET
3
ISHARE
4
6
EN/VFF1
EN/VFF2
FN6641 Rev.3.00
July 20, 2016
VCC
26
FB1
Page 3 of 39
ISL8120
Functional Pin Descriptions
(Continued)
PIN
NUMBER
5
SYMBOL
FSYNC
DESCRIPTION
The oscillator switching frequency is adjusted by placing a resistor (RFS) from this pin to GND. The internal oscillator will
lock to an external frequency source if this pin is connected to a switching square pulse waveform, typically the CLKOUT
input signal from another ISL8120 or an external clock. The internal oscillator synchronizes with the leading edge of the
input signal.
This pin has a dual function depending on the mode in which the chip is operating. It provides a clock signal to
synchronize with other ISL8120(s) with its VSEN2- pulled within 400mV of VCC for multiphase (3-, 4-, 6-, 8-, 10-, or
12-phase) operation. When the VSEN2- pin is not within 400mV of VCC, ISL8120 is in dual mode (dual independent
PWM output). The clockout signal of this pin is not available in this mode, however, the ISL8120 can be synchronized
to external clock. In dual mode, this pin works as the following two functions:
1. An external reference (0.6V target only) can be in place of the Channel 2’s internal reference through this pin for
DDR/tracking applications (see
“DDR and Dual Mode Operation” on page 35).
2. The ISL8120 operates as a dual-PWM controller for two independent regulators with selectable phase degree shift,
which is programmed by the voltage level on REFIN (see
“DDR and Dual Mode Operation” on page 35).
8
PGOOD
Provides an open drain power-good signal when both channels are within 9% of the nominal output regulation point
with 4% hysteresis (13%/9%) and soft-start complete. PGOOD monitors the outputs (VMON1/2) of the internal
differential amplifiers.
These pins are the inverting inputs of the error amplifiers. These pins should be connected to VMON1, VMON2 with the
compensation feedback network. No direct connection between FB and VMON pins is allowed. With VSEN2- pulled
within 400mV of VCC, the corresponding error amplifier is disabled and the amplifier’s output is high impedance. FB2
is one of the two pins to determine the relative phase relationship between the internal clock of both channels and the
CLKOUT signal. See
Table 1 on page 22.
These pins are outputs of the unity gain amplifiers. They are connected internally to the OV/UV/PGOOD comparators.
These pins should be connected to the FB1, FB2 pins by a standard feedback network when both channels are operating
independently. When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding differential amplifier is
disabled and its output (VMON pin) is high impedance. In such an event, the VMON pin can be used as an additional
monitor of the output voltage with a resistor divider to protect the system against single point of failure, which occurs
in the system using the same resistor divider for both of the UV/OV comparator and output voltage feedback.
These pins are the negative inputs of standard unity gain operational amplifier for differential remote sense for the
corresponding regulator (Channels 1and 2), and should be connected to the negative rail of the load/processor.
When VSEN1-, VSEN2- are pulled within 400mV of VCC, the corresponding error amplifier and differential amplifier are
disabled and their outputs are high impedance. Both VSEN2+ and FB2 input signal levels determine the relative phases
between the internal controllers as well as the CLKOUT signal. See
Table 1 on page 22.
When configured as multiple power modules (each module with independent voltage loop) operating in parallel, in
order to implement the current sharing control, a resistor (100Ω typical) needs to be inserted between the VSEN1- pin
and the output voltage negative sense point (between VSEN1- and lower voltage sense resistor), as shown in the “Typical
Application Circuits”
“Multiple Power Modules in Parallel with Current Sharing Control” on page 13.
This introduces a
correction voltage for the modules with lower load current to keep the current distribution balanced among modules.
The module with the highest load current will automatically become the master module. The recommended value for
the VSEN1- resistor is 100Ω and it should not be large in order to keep the unit gain amplifier input impedance
compatibility.
These pins are the positive inputs of the standard unity gain operational amplifier for differential remote sense for the
corresponding channel (Channels 1 and 2), and should be connected to the positive rail of the load/processor. These
pins can also provide precision output voltage trimming capability by pulling a resistor from this pin to the positive rail
of the load (trimming down) or the return (typical VSEN1-, VSEN2- pins) of the load (trimming up). The typical input
impedance of VSEN+ with respect to VSEN- is 600kΩ. By setting the resistor divider connected from the output voltage
to the input of the differential amplifier, the desired output voltage can be programmed. To minimize the system
accuracy error introduced by the input impedance of the differential amplifier, a resistor below 1k is recommended to
be used for the lower leg (ROS) of the feedback resistor divider.
With VSEN2- pulled within 400mV of VCC, the corresponding error amplifier is disabled and VSEN2+ is one of the two
pins to determine the relative phase relationship between the internal clock of both channels and the CLKOUT signal.
See
Table 1 on page 22
for details.
These pins are the inverting (-) inputs of the current sensing amplifiers to provide r
DS(ON)
, DCR, or precision resistor
current sensing together with the ISEN1A, ISEN2A pins. Refer to “Typical Application Circuits”
“2-Phase Operation with
DCR Sensing” on page 7
for DCR sensing set up and
“2-Phase Operation with r
DS(ON)
Sensing” on page 8
for r
DS(ON)
sensing set up.
7
CLKOUT/REFIN
32
10
FB1
FB2
31
11
VMON1
VMON2
30
12
VSEN1-
VSEN2-
29
13
VSEN1+
VSEN2+
28
14
ISEN1B
ISEN2B
FN6641 Rev.3.00
July 20, 2016
Page 4 of 39
ISL8120
Functional Pin Descriptions
(Continued)
PIN
NUMBER
27
15
16
SYMBOL
ISEN1A
ISEN2A
VIN
DESCRIPTION
These pins are the noninverting (+) inputs of the current sensing amplifiers to provide r
DS(ON)
, DCR, or precision resistor
current sensing together with the ISEN1B, ISEN2B pins.
This pin is the input of the internal linear regulator. It should be tied directly to the input rail. The internal linear device
is protected against reverse bias generated by the remaining charge of the decoupling capacitor at PVCC when losing
the input rail. When used with an external 3.3V to 5V supply, this pin should be tied directly to PVCC.
These pins provide the bootstrap biases for the high-side drivers. Internal bootstrap diodes connected to the PVCC pin
provide the necessary bootstrap charge. Its typical operational voltage range is 2.5V to 5.6V.
These pins provide the gate signals to drive the high-side devices and should be connected to the MOSFETs’ gates.
25
17
24
18
23
19
22
20
21
26
BOOT1
BOOT2
UGATE1
UGATE2
PHASE1
PHASE2
LGATE1
LGATE2
PVCC
VCC
Connect these pins to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. These pins represent
the return path for the high-side gate drives.
These pins provide the drive for the low-side devices and should be connected to the MOSFETs’ gates.
This pin is the output of the internal series linear regulator. It provides the bias for both low-side and high-side drives.
Its operational voltage range is 3V to 5.6V. The decoupling ceramic capacitor in the PVCC pin is 10µF.
This pin provides bias power for the analog circuitry. An RC filter is recommended between the connection of this pin to
a 3V to 5.6V bias (typically PVCC). R is suggested to be a 5Ω resistor. And in 3.3V applications, the R could be shorted
to allow the low end input in concerns of the VCC falling threshold. The VCC decoupling capacitor is strongly
recommended to be as large as a 10µF ceramic capacitor. This pin can be powered either by the internal linear regulator
or by an external voltage source.
The bottom pad is the signal and power ground plane. All voltage levels are referenced to this pad. This pad provides a
return path for the low-side MOSFET drives and internal power circuitries as well as all analog signals. Connect this pad
to the circuit ground with the shortest possible path (more than 5 to 6 vias to the internal ground plane, placed on the
soldering pad are recommended).
33
GND
Ordering Information
PART NUMBER
(Notes
3, 4)
ISL8120CRZ (Note
1)
ISL8120IRZ (Note
2)
PART
MARKING
ISL8120 CRZ
ISL8120 IRZ
TEMP. RANGE
(°C)
0 to +70
-40 to +85
PACKAGE
(RoHS COMPLIANT)
32 Ld QFN
32 Ld QFN
PKG.
DWG.#
L32.5x5B
L32.5x5B
1. Add “-T” suffix for 6000 unit Tape and Reel option. Please refer to
TB347
for details on reel specifications.
2. Add “-T” suffix for 6000 unit or “-TK” suffix for 1000 unit Tape and Reel options. Please refer to
TB347
for details on reel specifications.
3. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
4. For Moisture Sensitivity Level (MSL), please see device information page for
ISL8120.
For more information on MSL please see techbrief
TB363.
FN6641 Rev.3.00
July 20, 2016
Page 5 of 39
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