IS49RL36320-093FBL datasheet, PDF

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IS49RL36320-093FBL: DescriptionDDR DRAM,; Categorystorage storage; File Size6MB，122 Pages; ManufacturerIntegrated Silicon Solution ( ISSI )

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IS49RL36320-093FBL Overview

DDR DRAM,

IS49RL36320-093FBL Parametric

Parameter Name	Attribute value
Maker	Integrated Silicon Solution ( ISSI )
package instruction	LBGA,
Reach Compliance Code	unknown
access mode	MULTI BANK PAGE BURST
Other features	AUTO REFRESH
JESD-30 code	S-PBGA-B168
length	13.5 mm
memory density	1207959552 bit
Memory IC Type	DDR DRAM
memory width	36
Number of functions	1
Number of ports	1
Number of terminals	168
word count	33554432 words
character code	32000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	95 °C
Minimum operating temperature
organize	32MX36
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Maximum seat height	1.25 mm
Maximum supply voltage (Vsup)	1.42 V
Minimum supply voltage (Vsup)	1.28 V
surface mount	YES
technology	CMOS
Temperature level	OTHER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	13.5 mm
Base Number Matches	1

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1Gb: x18, x36 RLDRAM 3

Features

RLDRAM 3

Features

IS49RL18640-4 Meg x 18 x 16 Banks

IS49RL36320–2 Meg x 36 x 16 Banks

Options

• Clock cycle and

RC timing

•

1200

MHz DDR operation (2400 Mb/s/ball

data rate)

• Organization

–

64 Meg x 18, and 32 Meg x 36 common I/O (CIO)

–

16 banks

• 1.2V center-terminated push/pull I/O

•

2.5V V

EXT

, 1.35V V

, 1.2V V

DDQ

(optional 1.35V V

DDQ

for 2400 operation only).

•

• SDR addressing

• Programmable READ/WRITE latency (RL/WL) and

burst length

• Data mask for WRITE commands

•

• Fr

x#)

and output data clocks (QK

x#)

• On-die DLL generates CK edge-aligned data and

•

64ms refresh (128K refresh per 64ms)

168-ball FBGA package

40 Ω or 60 Ω matched

impedance outputs

Integrated on-die termination (ODT)

Single or multibank writes

Extended operating range (200–1200 MHz)

Reduced

cycle time (

RC (MIN) = 6.67 - 8ns)

–

0.83

ns and

RC (MIN) =

6.67ns

(RL3-2400)

for -083F

–

0.83

ns and

RC (MIN) =

7.5ns

(RL3-2400)

for -083E

–

0.93

ns and

RC (MIN) =

7.5ns

(RL3-2133)

for -093F

–

0.93

ns and

RC (MIN) =

8ns

(RL3-2133)

for -093E

– 1.07ns and

RC (MIN) =

8ns

(RL3-1866)

for -107E

•

- 64 Meg x 18

- 32 Meg x 36

Operating Temperature

– Commercial (T

= 0° to +95°C)

– Industrial (T

= –40°C to +95°C)

Package

– 168-ball FBGA (Pb-free)

•

• READ training register

• Multiplexed and non-multiplexed addressing capa-

bilities

• Mirror function

• Output driver and ODT calibration

•

Post Package Repar - 1 row per half bank

• JTAG interface (IEEE 1149.1-2001)

no ce. ISSI assumes no liability arising out of the applica on or use of any informa on, products or services described herein. Customers are advised to obtain the

latest version of this device speciﬁca on before relying on any published informa on and before placing orders for prodsu.c t

Integrated Silicon Solu on, Inc. does not recommend the use of any of its products in life support applica ons where the failure or malfunc on of the product can

reasonably be expected to cause failure of the life support system or to signiﬁcantly aﬀect its safety or eﬀec veness. Products are not authorized for use in such

applica ons unless Integrated Silicon Solu on, Inc. receives wri en assurance to its sa sfac on, that:

a.) the risk of injury or damage has been minimized;

b.) the user assume all such risks; and

c.) poten al liability of Integrated Silicon Solu on, Inc is adequately protected under the circumstances

RLDRAM® is a registered trademark of Micron Technology, Inc.

www.issi.com

Rev.00C

09/18/2019

1Gb

: x18, x36 RLDRAM 3

Contents

General Description .........................................................................................................................................

General Notes ..............................................................................................................................................

State Diagram ................................................................................................................................................

Functional Block Diagrams ............................................................................................................................. 11

Ball Assignments and Descriptions ................................................................................................................. 13

Electrical Characteristics – I

Specifications .................................................................................................. 17

Electrical Specifications – Absolute Ratings and I/O Capacitance .....................................................................

Absolute Maximum Ratings ........................................................................................................................

Input/Output Capacitance ..........................................................................................................................

AC and DC Operating Conditions .................................................................................................................... 22

AC Overshoot/Undershoot Specifications .................................................................................................... 23

Slew Rate Definitions for Single-Ended Input Signals ................................................................................... 27

Slew Rate Definitions for Differential Input Signals ...................................................................................... 29

ODT Characteristics .......................................................................................................................................

ODT Resistors ............................................................................................................................................

ODT Sensitivity ..........................................................................................................................................

Output Driver Impedance ...............................................................................................................................

Output Driver Sensitivity ............................................................................................................................

Output Characteristics and Operating Conditions ............................................................................................

Reference Output Load ...............................................................................................................................

Slew Rate Definitions for Single-Ended Output Signals .....................................................................................

Slew Rate Definitions for Differential Output Signals ........................................................................................

Speed Bin Tables ............................................................................................................................................

AC Electrical Characteristics ...........................................................................................................................

Temperature and Thermal Impedance Characteristics .....................................................................................

Command and Address Setup, Hold, and Derating ...........................................................................................

Data Setup, Hold, and Derating .......................................................................................................................

Commands ....................................................................................................................................................

MODE REGISTER SET (MRS) Command .........................................................................................................

Mode Register 0 (MR0) ....................................................................................................................................

RC .............................................................................................................................................................

Data Latency ..............................................................................................................................................

DLL Enable/Disable ...................................................................................................................................

Address Multiplexing ..................................................................................................................................

Mode Register 1 (MR1) ....................................................................................................................................

Output Drive Impedance ............................................................................................................................

DQ On-Die Termination (ODT) ...................................................................................................................

DLL Reset ...................................................................................................................................................

ZQ Calibration ............................................................................................................................................

ZQ Calibration Long ...................................................................................................................................

ZQ Calibration Short ...................................................................................................................................

AUTO REFRESH Protocol ............................................................................................................................

Burst Length (BL) .......................................................................................................................................

Mode Register 2 (MR2) ....................................................................................................................................

READ Training Register (RTR) .....................................................................................................................

WRITE Protocol ..........................................................................................................................................

WRITE Command ..........................................................................................................................................

Multibank WRITE .......................................................................................................................................

Post Package Repair – PPR .............................................................................................................................. 79

PPR Row Repair Sequence .......................................................................................................................... 79

READ Command ............................................................................................................................................

www.issi.com

Rev.00C

09/18/2019

1Gb: x18, x36 RLDRAM 3

Contents

............................................................................................................................

AUTO REFRESH Command

............................................................................................................................

INITIALIZATION Operation

WRITE Operation ...............................................................................................................................................

READ Operation .................................................................................................................................................

..............................................................................................................................

AUTO REFRESH Operation

RESET Operation .................................................................................................................................................

Mirror Function ...................................................................................................................................................

Multiplexed Address Mode ...............................................................................................................................

100

........................................................................................... 105

Data Latency in Multiplexed Address Mode

............................................................................ 105

REFRESH Command in Multiplexed Address Mode

....................................................................................................

IEEE 1149.1 Serial Boundary Scan (JTAG)

Disabling the JTAG Feature .........................................................................................................................

Test Access Port (TAP) ..................................................................................................................................

TAP Controller ...............................................................................................................................................

Performing a TAP RESET ..............................................................................................................................

TAP Registers ..................................................................................................................................................

TAP Instruction Set ........................................................................................................................................

109

110

112

113

Ordering Information

............................................................................................................ ..121

Package Dimensions ........................................................................................................... 122

www.issi.com

Rev.00C

09/18/2019

1Gb:

x18, x36 RLDRAM 3

Figures

List of Figures

Figure 1:

Figure 2:

Figure 3:

Figure

1Gb

RLDRAM

3 Part Numbers .............................................................................. ....................... 2

Simplified State Diagram ..................................................................................................................10

Meg x 18 Functional Block Diagram ............................................................................................. 11

Meg x 36 Functional Block Diagram ............................................................................................. 13

Figure

Single-Ended Input Signal ............................................................................................................... 22

Figure

Overshoot ....................................................................................................................................... 23

Figure

Undershoot .................................................................................................................................... 23

Figure

for Differential Signals ................................................................................................................ 24

Figure

Single-Ended Requirements for Differential Signals ........................................................................ 25

Figure

10:

Definition of Differential AC Swing and

DVAC ................................................................................26

Figure

11:

Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 27

Figure 12: Nominal Slew Rate Definition for Single-Ended Input Signals .......................................................... 27

Figure 13: Nominal Differential Input Slew Rate Definition for CK, CK#, DKx, and DKx# .................................. 28

Figure 14: ODT Levels and I-V Characteristics ................................................................................................

Figure 15: Output Driver ................................................................................................................................

Figure 16: DQ Output Signal ..........................................................................................................................

Figure 17: Differential Output Signal ..............................................................................................................

Figure 18: Reference Output Load for AC Timing and Output Slew Rate ...........................................................

Figure 19: Nominal Slew Rate Definition for Single-Ended Output Signals .......................................................

Figure 20: Nominal Differential Output Slew Rate Definition for QKx, QKx# .....................................................

Figure 21: Example Temperature Test Point Location ......................................................................................

Figure 22: Nominal Slew Rate and

VAC for

IS (Command and Address - Clock) ...............................................

Figure 23: Nominal Slew Rate for

IH (Command and Address - Clock) ............................................................

Figure 24: Tangent Line for

IS (Command and Address - Clock) ......................................................................

Figure 25: Tangent Line for

IH (Command and Address - Clock) .....................................................................

Figure 26: Nominal Slew Rate and

VAC for

DS (DQ - Strobe) ..........................................................................

Figure 27: Nominal Slew Rate for

DH (DQ - Strobe) ........................................................................................

Figure 28: Tangent Line for

DS (DQ - Strobe) .................................................................................................

Figure 29: Tangent Line for

DH (DQ - Strobe) ................................................................................................

Figure 30: MRS Command Protocol ...............................................................................................................

Figure 31: MR0 Definition for Non-Multiplexed Address Mode ........................................................................

Figure 32: MR1 Definition for Non-Multiplexed Address Mode ........................................................................

Figure 33: ZQ Calibration Timing (ZQCL and ZQCS) .......................................................................................

Figure 34: Read Burst Lengths ........................................................................................................................

Figure 35: MR2 Definition for Non-Multiplexed Address Mode ........................................................................

Figure 36: READ Training Function - Back-to-Back Readout ............................................................................

Figure

37:

WRITE Command .........................................................................................................................

Figure

38:

Entry, Repair, and Exit Timing Diagram ........................................................................................

Figure 39:

Figure

40:

Figure 41:

Figure 42:

Figure 43:

Figure 44:

Figure 45:

Figure 46:

Figure 47:

Figure 48:

Figure 49:

Figure

50:

Figure 51:

READ Command ...........................................................................................................................

Bank Address-Controlled AUTO REFRESH Command .....................................................................

Multibank AUTO REFRESH Command ...........................................................................................

Power-Up/Initialization Sequence ...............................................................................................

WRITE Burst .................................................................................................................................

Consecutive WRITE Bursts .............................................................................................................

WRITE-to-READ ............................................................................................................................

WRITE - DM Operation ..................................................................................................................

Consecutive Quad Bank WRITE Bursts ...........................................................................................

Interleaved READ and Quad Bank WRITE Bursts .............................................................................

Basic READ Burst ..........................................................................................................................

Consecutive READ Bursts (BL = 2) ..................................................................................................

Consecutive READ Bursts (BL = 4) ..................................................................................................

www.issi.com

Rev.00C

09/18/2019

IS49RL36320-093FBL Related Products

	IS49RL36320-093FBL	IS49RL36320-093FBLI	IS49RL36320-093EBL	IS49RL36320-093EBLI	IS49RL36320-083FBL	IS49RL36320-083FBLI	IS49RL36320-107EBL	IS49RL36320-107EBLI	IS49RL36320-083EBL	IS49RL36320-083EBLI
Description	DDR DRAM,	DDR DRAM,	DDR DRAM,	DDR DRAM,	DDR DRAM,	DDR DRAM,	DDR DRAM,	DDR DRAM,	DDR DRAM,	DDR DRAM,
Maker	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )	Integrated Silicon Solution ( ISSI )
package instruction	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,	LBGA,
Reach Compliance Code	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknown	unknow	unknow
access mode	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST	MULTI BANK PAGE BURST
Other features	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH	AUTO REFRESH
JESD-30 code	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168	S-PBGA-B168
length	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm
memory density	1207959552 bit	1207959552 bit	1207959552 bit	1207959552 bit	1207959552 bit	1207959552 bit	1207959552 bit	1207959552 bit	1207959552 bi	1207959552 bi
Memory IC Type	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM	DDR DRAM
memory width	36	36	36	36	36	36	36	36	36	36
Number of functions	1	1	1	1	1	1	1	1	1	1
Number of ports	1	1	1	1	1	1	1	1	1	1
Number of terminals	168	168	168	168	168	168	168	168	168	168
word count	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words	33554432 words
character code	32000000	32000000	32000000	32000000	32000000	32000000	32000000	32000000	32000000	32000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C	95 °C
organize	32MX36	32MX36	32MX36	32MX36	32MX36	32MX36	32MX36	32MX36	32MX36	32MX36
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA	LBGA
Package shape	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE	SQUARE
Package form	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE	GRID ARRAY, LOW PROFILE
Maximum seat height	1.25 mm	1.25 mm	1.25 mm	1.25 mm	1.25 mm	1.25 mm	1.25 mm	1.25 mm	1.25 mm	1.25 mm
Maximum supply voltage (Vsup)	1.42 V	1.42 V	1.42 V	1.42 V	1.42 V	1.42 V	1.42 V	1.42 V	1.42 V	1.42 V
Minimum supply voltage (Vsup)	1.28 V	1.28 V	1.28 V	1.28 V	1.28 V	1.28 V	1.28 V	1.28 V	1.28 V	1.28 V
surface mount	YES	YES	YES	YES	YES	YES	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS	CMOS
Temperature level	OTHER	INDUSTRIAL	OTHER	INDUSTRIAL	OTHER	INDUSTRIAL	OTHER	INDUSTRIAL	OTHER	INDUSTRIAL
Terminal form	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL	BALL
Terminal pitch	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm	1 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm	13.5 mm

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Shortcut: 00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W

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