Smallest footprint in chip-scale (CSP): 1.5 x 0.8 mm
Ultra-low power: <1 µA
Supports coin-cell or super-cap battery backup voltages
Vdd supply range: 1.5V to 3.63V over -40°C to +85°C
Oscillator output eliminates external load caps
NanoDrive™ programmable output swing for lowest power
Internal filtering eliminates external Vdd bypass cap
Fixed 32.768 kHz
<10 ppm initial stability
<100 ppm stability over -40°C to +85°C
Pb-free, RoHS and REACH compliant
Mobile Phones
Tablets
Health and Wellness Monitors
Fitness Watches
Sport Video Cams
Wireless Keypads
Ultra-Small Notebook PC
Pulse-per-Second (pps) Timekeeping
RTC Reference Clock
Battery Management Timekeeping
Electrical Characteristics
Parameter
Fixed Output Frequency
Symbol
Fout
Min.
Typ.
32.768
Max.
Unit
kHz
Frequency Stability
10
75
Frequency Stability
[2]
Condition
Frequency and Stability
T
A
= 25°C, post reflow, includes underfill, Vdd: 1.5V – 3.63V.
Tested with Agilent 53132A freq. counter, gate time
≥
100ms.
ppm
T
A
= -10°C to +70°C, Vdd: 1.5V – 3.63V. Stability includes initial,
power supply, and temperature stability components.
T
A
= -40°C to +85°C, Vdd: 1.5V – 3.63V. Stability includes initial,
power supply, and temperature stability components.
T
A
= -10°C to +70°C, Vdd: 1.2V – 1.5V. Stability includes initial,
power supply, and temperature stability components.
ppm
V
V
1st Year
T
A
= -10°C to +70°C
T
A
= -40°C to +85°C
T
A
= 25°C, Vdd: 1.5V – 2.5V. No load
T
A
= -10°C to +70°C, Vdd max: 3.63V. No load
T
A
= -40°C to +85°C, Vdd max: 3.63V. No load
μA/Vpp
ms
ms
°C
°C
T
A
= -40°C to +85°C, Vdd: 1.5V – 3.63V. No load
Vdd Ramp-up 0 to 90%, T
A
= -40°C to +85°C
T
A
= -40°C to +85°C
F_stab
100
250
25°C Aging
-3
1.2
1.5
0.90
3
3.63
3.63
Supply Voltage and Current Consumption
Operating Supply Voltage
Vdd
Core Operating Current
[3, 4]
Idd
1.3
1.4
μA
Output Stage Operating Current
[3]
Power-Supply Ramp
T
START-UP
at Power-up
Commercial Temperature
Industrial Temperature
Idd_out
t_Vdd_
Ramp
T_start
-10
-40
0.065
0.125
100
150
300
70
85
Operating Temperature Range
T_use
Notes:
1. Stability is specified for two operating voltage ranges. Stability progressively degrades with supply voltage below 1.5V. Frequency tests are performed with an
Agilent 53132A frequency counter with >100ms gate time.
2. Core operating current does not include output driver operating current or load current.
3. To derive total operating current (no load), add core operating current + (0.065 µA/V) * (output voltage swing).
SiTime Corporation
Rev 0.90
990 Almanor Avenue, Sunnyvale, CA 94085
(408) 328-4400
www.sitime.com
Revised March 7, 2014
SiT1532
Smallest Footprint (1.2mm
2
), Ultra-Low Power 32.768 kHz
Oscillator in CSP
The Smart Timing Choice
The Smart Timing Choice
Electrical Characteristics
(continued)
Parameter
Output Rise/Fall Time
Output Clock Duty Cycle
Output Voltage High
Output Voltage Low
Symbol
tr, tf
DC
VOH
VOL
48
90%
10%
Min.
Typ.
100
Max.
200
52
Unit
ns
%
V
V
Vdd: 1.5V – 3.63V. I
OH
= -10
μA,
15 pF
Vdd: 1.5V – 3.63V. I
OL
= 10
μA,
15 pF
Condition
LVCMOS Output Option, T
A
= -40°C to +85°C, typical values are at T
A
= 25°C
10-90%, 15 pF load, Vdd = 1.5V to 3.63V
NanoDrive™ Programmable, Reduced Swing Output
Output Rise/Fall Time
Output Clock Duty Cycle
AC-coupled Programmable
Output Swing
DC-Biased Programmable
Output Voltage High Range
DC-Biased Programmable
Output Voltage Low Range
Programmable Output Voltage
Swing Tolerance
Period Jitter
T_jitt
tf, tf
DC
V_sw
48
0.20 to
0.80
0.60 to
1.225
0.35 to
0.80
-0.055
35
0.055
200
52
ns
%
V
SiT1532 does not internally AC-couple. This output description
is intended for a receiver that is AC-coupled. See Table 2 for
acceptable NanoDrive swing options.
Vdd: 1.5V – 3.63V, 10 pF Load, I
OH
/ I
OL
= ±0.2
μA.
Vdd: 1.5V – 3.63V. I
OH
= -0.2
μA,
10 pF Load. See Table 1 for
acceptable V
OH
/V
OL
setting levels.
Vdd: 1.5V – 3.63V. I
OL
= 0.2
μA,
10 pF Load. See Table 1 for
acceptable V
OH
/V
OL
setting levels.
T
A
= -40°C to +85°C, Vdd = 1.5V to 3.63V. See Tables 1 and -2
for acceptable NanoDrive Settings.
N = 10,000, T
A
= 25°C, Vdd = 1.5V – 3.63V
30-70%, 10 pF Load
VOH
VOL
V
V
V
ns
RMS
Pin Configuration
Pin
1, 4
Symbol
GND
I/O
Power Supply
Ground
Functionality
Connect to ground. Acceptable to connect pin 1 and 4 together. Both pins
must be connected to GND.
Oscillator clock output. The CLK can drive into a Ref CLK input or into an
ASIC or chip-set’s 32kHz XTAL input. When driving into an ASIC or
chip-set oscillator input (X IN and X Out), the CLK Out is typically
connected directly to the XTAL IN pin. No need for load
capacitors. The output driver is intended to be insensitive to capacitive
loading.
CSP Package (Top View)
2
CLK Out
OUT
GND
1
4
GND
3
Vdd
Connect to power supply 1.2V
≤
Vdd
≤
3.63V. Under normal operating
conditions, Vdd does not require external bypass/decoupling
capacitor(s). For more information about the internal power-supply
Power Supply filtering, see the
Power Supply Noise Immunity
section in the detailed
description.
Contact factory for applications that require a wider operating supply
voltage range.
C LK O ut
2
3
Vdd
Rev. 0.90
Page 2 of 10
www.sitime.com
SiT1532
Smallest Footprint (1.2mm
2
), Ultra-Low Power 32.768 kHz
Oscillator in CSP
The Smart Timing Choice
The Smart Timing Choice
System Block Diagram
MEMS Resonator
GND
Control
Regulators
Vdd
Trim
Prog
Prog
GND
Sustaining
Amp
Ultra-Low
Power
PLL
Divider
Ultra-Low
Power Driver
CLK Out
Figure 1.
Absolute Maximum
Attempted operation outside the absolute maximum ratings of may cause permanent damage to the part. Actual performance of
the IC is only guaranteed within the operational specifications, not at absolute maximum ratings.
Parameter
Continuous Power Supply Voltage Range (Vdd)
Short Duration Maximum Power Supply Voltage (Vdd)
Continuous Maximum Operating Temperature Range
Short Duration Maximum Operating Temperature Range
Human Body Model ESD Protection
Charge-Device Model (CDM) ESD Protection
Machine Model (MM) ESD Protection
Latch-up Tolerance
Mechanical Shock Resistance
Mechanical Vibration Resistance
1508 CSP Junction Temperature
Mil 883, Method 2002
Mil 883, Method 2007
<30 minutes
Vdd = 1.5V - 3.63V
Vdd = 1.5V - 3.63V,
≤30
mins
HBM, JESD22-A114
JESD220C101
T
A
= 25°C
JESD78 Compliant
10,000
70
150
g
g
°C
Test Condition
Value
-0.5 to 3.63
4.0
105
125
2000
500
200
Unit
V
V
°C
°C
V
V
V
Thermal Consideration
Package
1508 CSP
JA, 4 Layer Board
(°C/W)
TBD
JA, 2 Layer Board
(°C/W)
JC, Bottom
(°C/W)
Rev. 0.90
Page 3 of 10
www.sitime.com
SiT1532
Smallest Footprint (1.2mm
2
), Ultra-Low Power 32.768 kHz
Oscillator in CSP
The Smart Timing Choice
The Smart Timing Choice
Description
The SiT1532 is the world’s smallest, lowest power 32 kHz
oscillator optimized for mobile and other battery-powered
applications. SiTime’s silicon MEMS technology enables the
smallest footprint and chip-scale packaging. This device
reduces the 32 kHz footprint by as much as 85% compared to
existing 2.0 x 1.2 mm SMD XTAL packages. Unlike XTALs, the
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