IDT70T631S10BC8 datasheet, PDF

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IDT70T631S10BC8: DescriptionDual-Port SRAM, 256KX18, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256; Categorystorage storage; File Size338KB，27 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT70T631S10BC8 Overview

Dual-Port SRAM, 256KX18, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256

IDT70T631S10BC8 Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Parts packaging code	BGA
package instruction	17 X 17 MM, 1.40 MM HEIGHT, 1 MM PITCH, BGA-256
Contacts	256
Reach Compliance Code	not_compliant
ECCN code	3A991
Maximum access time	10 ns
I/O type	COMMON
JESD-30 code	S-PBGA-B256
JESD-609 code	e0
length	17 mm
memory density	4718592 bit
Memory IC Type	DUAL-PORT SRAM
memory width	18
Humidity sensitivity level	3
Number of functions	1
Number of ports	2
Number of terminals	256
word count	262144 words
character code	256000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	256KX18
Output characteristics	3-STATE
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA256,16X16,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	225
power supply	2.5,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum standby current	0.01 A
Minimum standby current	2.4 V
Maximum slew rate	0.405 mA
Maximum supply voltage (Vsup)	2.6 V
Minimum supply voltage (Vsup)	2.4 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	17 mm
Base Number Matches	1

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Features

◆

HIGH-SPEED 2.5V

512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

◆

IDT70T633/1S

◆

True Dual-Port memory cells which allow simultaneous

access of the same memory location

High-speed access

– Commercial: 8/10/12/15ns (max.)

– Industrial: 10/12ns (max.)

RapidWrite Mode simplifies high-speed consecutive write

cycles

Dual chip enables allow for depth expansion without

external logic

IDT70T633/1 easily expands data bus width to 36 bits or

more using the Master/Slave select when cascading more

than one device

M/S = V

for

BUSY

output flag on Master,

M/S = V

for

BUSY

input on Slave

Busy and Interrupt Flags

◆

Full hardware support of semaphore signaling between

ports on-chip

On-chip port arbitration logic

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus

matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1 in

BGA-208 and BGA-256 packages

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)

power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 144-pin Thin Quad

Flatpack and 208-ball fine pitch Ball Grid Array

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Functional Block Diagram

Dout0-8_L

Dout9-17_L

Dout0-8_R

Dout9-17_R

512/256K x 18

MEMORY

ARRAY

I/O

- I/O

17L

Din_L

Din_R

I/O

- I/O

17R

18L

(1)

Address

Decoder

ADDR_L

ADDR_R

Address

Decoder

18R

(1)

TDI

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

TDO

JTAG

TCK

TMS

TRST

R/W

BUSY

L(2,3)

SEM

INT

L(3)

(4)

BUSY

R(2,3)

M/S

SEM

INT

R(3)

NOTES:

LOGIC

1. Address A

x is a NC for IDT70T631.

BUSY

is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and

INT

are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx,

INTx,

M/S and the

sleep mode pins themselves (ZZx) are not affected during sleep mode.

CONTROL

(4)

5670 drw 01

APRIL 2004

DSC-5670/4

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