74AUP2G08GN,115 datasheet, PDF

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74AUP2G08GN,115: Descriptionlogic gates dual 2-input and gate; Categorylogic logic; File Size281KB，21 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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74AUP2G08GN,115 Overview

logic gates dual 2-input and gate

74AUP2G08GN,115 Parametric

Parameter Name	Attribute value
Brand Name	NXP Semiconductor
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	SON
package instruction	1.2 X 1 MM, 0.35 MM HEIGHT, SOT1116, SON-8
Contacts	8
Manufacturer packaging code	SOT1116
Reach Compliance Code	compliant

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74AUP2G08

Low-power dual 2-input AND gate

Rev. 7 — 18 January 2013

Product data sheet

1. General description

The 74AUP2G08 provides the dual 2-input AND function.

Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall

times across the entire V

range from 0.8 V to 3.6 V.

This device ensures a very low static and dynamic power consumption across the entire

range from 0.8 V to 3.6 V.

This device is fully specified for partial power-down applications using I

OFF

. The I

OFF

circuitry disables the output, preventing a damaging backflow current through the device

when it is powered down.

2. Features and benefits



Wide supply voltage range from 0.8 V to 3.6 V



High noise immunity



Complies with JEDEC standards:



JESD8-12 (0.8 V to 1.3 V)



JESD8-11 (0.9 V to 1.65 V)



JESD8-7 (1.2 V to 1.95 V)



JESD8-5 (1.8 V to 2.7 V)



JESD8-B (2.7 V to 3.6 V)



ESD protection:



HBM JESD22-A114F Class 3A exceeds 5000 V



MM JESD22-A115-A exceeds 200 V



CDM JESD22-C101E exceeds 1 000 V



Low static power consumption; I

= 0.9

A

(maximum)



Latch-up performance exceeds 100 mA per JESD78 Class II



Inputs accept voltages up to 3.6 V



Low noise overshoot and undershoot < 10 % of V



OFF

circuitry provides partial power-down mode operation



Multiple package options



Specified from

40 C

to +85

C

and

40 C

to +125

C

74AUP2G08GN,115 Related Products

	74AUP2G08GN,115	74AUP2G08GD,125
Description	logic gates dual 2-input and gate	logic gates and gate 2-element 2-IN cmos 8-pin
Brand Name	NXP Semiconductor	NXP Semiconduc
Is it Rohs certified?	conform to	conform to
Maker	NXP	NXP
Parts packaging code	SON	SON
package instruction	1.2 X 1 MM, 0.35 MM HEIGHT, SOT1116, SON-8	3 X 2 MM, 0.50 MM HEIGHT, PLASTIC, SOT996-2, XSON-8
Contacts	8	8
Manufacturer packaging code	SOT1116	SOT996-2
Reach Compliance Code	compliant	compli

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