DS1243Y-120 datasheet, PDF - EEWORLD Datasheet

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DS1243Y-120: Description0 TIMER(S), REAL TIME CLOCK, PDIP28; CategoryThe embedded processor and controller Microcontrollers and processors; File Size230KB，13 Pages; ManufacturerDALLAS; Websitehttp://www.dalsemi.com

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DS1243Y-120 Overview

0 TIMER(S), REAL TIME CLOCK, PDIP28

DS1243Y-120 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	DALLAS
package instruction	DIP, DIP28,.6
Reach Compliance Code	unknow
External data bus width	8
Information access methods	SERIAL, FIXED PROTOCOL
interrupt capability	N
JESD-30 code	R-PDIP-T28
JESD-609 code	e0
Number of terminals	28
Number of timers
On-chip data RAM width	8
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	DIP
Encapsulate equivalent code	DIP28,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Certification status	Not Qualified
RAM (number of words)	4096
Maximum slew rate	85 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
shortest time	1/100 SECOND
Volatile	NO
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK

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DS1243Y

64K NV SRAM with Phantom Clock

www.dalsemi.com

FEATURES

Real time clock keeps track of hundredths of

seconds, seconds, minutes, hours, days, date

of the month, months, and years

8K x 8 NV SRAM directly replaces volatile

static RAM or EEPROM

Embedded lithium energy cell maintains

calendar operation and retains RAM data

Watch function is transparent to RAM

operation

Month and year determine the number of days

in each month; valid up to 2100

Lithium energy source is electrically

disconnected to retain freshness until power is

applied for the first time

Standard 28–pin JEDEC pinout

Full ±10% operating range

Operating temperature range 0°C to 70°C

Accuracy is better than ±1 minute/month @

25°C

Over 10 years of data retention in the absence

of power

Available in 120, 150 and 200 ns access time

PIN ASSIGNMENT

RST

A12

DQ0

DQ1

DQ2

GND

A11

A10

DQ7

DQ6

DQ5

DQ4

DQ3

28-Pin Encapsulated Package

720-Mil Extended

PIN DESCRIPTION

–A

GND

–DQ

ORDERING INFORMATION

DS1243Y–XXX

–120 120 ns access

–150 150 ns access

200 ns access

RST

– Address Inputs

– Chip Enable

– Ground

– Data In/Data Out

– Power (+5V)

– Write Enable

– Output Enable

– No Connect

– Reset

DS1243Y

DESCRIPTION

The DS1243Y 64K NV SRAM with Phantom Clock is a fully static nonvolatile RAM (organized as 8192

words by 8 bits) with a built–in real time clock. The DS1243Y has a self–contained lithium energy source

and control circuitry which constantly monitors V

for an out–of–tolerance condition. When such a

condition occurs, the lithium energy source is automatically switched on and write protection is

unconditionally enabled to prevent corrupted data in both the memory and real time clock.

1 of 13

080299

DS1243Y

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control

of Chip Enable (

), Output Enable (

), and Write Enable (

). Initially, a read cycle to any memory

location using the

and

control of the Phantom Clock starts the pattern recognition sequence by

moving a pointer to the first bit of the 64–bit comparison register. Next, 64 consecutive write cycles are

executed using the

and

control of the SmartWatch. These 64 write cycles are used only to gain

access to the Phantom Clock. Therefore, any address to the memory in the socket is acceptable.

However, the write cycles generated to gain access to the Phantom Clock are also writing data to a

location in the mated RAM. The preferred way to manage this requirement is to set aside just one address

location in RAM as a Phantom Clock scratch pad. When the first write cycle is executed, it is compared

to bit 0 of the 64–bit comparison register. If a match is found, the pointer increments to the next location

of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not

advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern

recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern

recognition continues for a total of 64 write cycles as described above until all the bits in the comparison

Phantom Clock is enabled and data transfer to or from the timekeeping registers can proceed. The next 64

cycles will cause the Phantom Clock to either receive or transmit data on DQ0, depending on the level of

the

pin or the

pin. Cycles to other locations outside the memory block can be interleaved with

cycles without interrupting the pattern recognition sequence or data transfer sequence to the Phantom

Clock.

PHANTOM CLOCK

The Phantom Clock information is contained in 8 registers of 8 bits, each of which is sequentially

accessed 1 bit at a time after the 64–bit pattern recognition sequence has been completed. When updating

the Phantom Clock registers, each register must be handled in groups of 8 bits. Writing and reading

individual bits within a register could produce erroneous results. These read/write registers are defined in

Figure 2.

Data contained in the Phantom Clock register is in binary coded decimal format (BCD). Reading and

writing the registers is always accomplished by stepping through all 8 registers, starting with bit 0 of

3 of 13

DS1243Y-120 Related Products

	DS1243Y-120	DS1243Y	DS1243Y-150	DS1243
Description	0 TIMER(S), REAL TIME CLOCK, PDIP28	0 TIMER(S), REAL TIME CLOCK, PDIP28	0 TIMER(S), REAL TIME CLOCK, PDIP28	0.05uV/C max, Single-Supply CMOS Operational Amplifier 10-MSOP -40 to 125
Is it Rohs certified?	incompatible	incompatible	incompatible	-
package instruction	DIP, DIP28,.6	0.720 INCH, PLASTIC, DIP-28	0.720 INCH, PLASTIC, DIP-28	-
Reach Compliance Code	unknow	unknow	unknow	-
External data bus width	8	8	8	-
Information access methods	SERIAL, FIXED PROTOCOL	SERIAL, FIXED PROTOCOL	SERIAL, FIXED PROTOCOL	-
interrupt capability	N	N	N	-
JESD-30 code	R-PDIP-T28	R-PDIP-T28	R-PDIP-T28	-
JESD-609 code	e0	e0	e0	-
Number of terminals	28	28	28	-
On-chip data RAM width	8	8	8	-
Maximum operating temperature	70 °C	70 °C	70 °C	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	DIP	DIP	DIP	-
Encapsulate equivalent code	DIP28,.6	DIP28,.6	DIP28,.6	-
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	-
Package form	IN-LINE	IN-LINE	IN-LINE	-
Certification status	Not Qualified	Not Qualified	Not Qualified	-
RAM (number of words)	4096	8000	8000	-
Maximum slew rate	85 mA	85 mA	85 mA	-
Maximum supply voltage	5.5 V	5.5 V	5.5 V	-
Minimum supply voltage	4.5 V	4.5 V	4.5 V	-
Nominal supply voltage	5 V	5 V	5 V	-
surface mount	NO	NO	NO	-
technology	CMOS	CMOS	CMOS	-
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	THROUGH-HOLE	THROUGH-HOLE	THROUGH-HOLE	-
Terminal pitch	2.54 mm	2.54 mm	2.54 mm	-
Terminal location	DUAL	DUAL	DUAL	-
shortest time	1/100 SECOND	1/100 SECOND	1/100 SECOND	-
Volatile	NO	NO	NO	-
uPs/uCs/peripheral integrated circuit type	TIMER, REAL TIME CLOCK	TIMER, REAL TIME CLOCK	TIMER, REAL TIME CLOCK	-

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