MOSEL VITELIC
V53C518165A
1M x 16 EDO PAGE MODE
CMOS DYNAMIC RAM
OPTIONAL SELF REFRESH
HIGH PERFORMANCE
Max. RAS Access Time, (t
RAC
)
Max. Column Address Access Time, (t
CAA
)
Min. Extended Data Out Page Mode Cycle Time, (t
PC
)
Min. Read/Write Cycle Time, (t
RC
)
50
50 ns
25 ns
20 ns
84 ns
60
60 ns
30 ns
25 ns
104 ns
Features
s
1MB x 16-bit organization
s
EDO Page Mode for a sustained data rate
of 50 MHz
s
RAS access time: 50, 60 ns
s
Dual CAS Inputs
s
Low power dissipation
s
Read-Modify-Write, RAS-Only Refresh,
CAS-Before-RAS Refresh
• Refresh Interval: 1024 cycles/16 ms
s
Available in 42-pin 400 mil SOJ and
44/50-pin 400 mil TSOP-II Packages
s
Single 5V
±10%
Power Supply
s
TTL Interface
s
Optional Self Refresh (V53C518165AS)
• Refresh Interval: 1024 cycles/128 ms
Description
The V53C518165A is a 1048576 x 16 bit high-
performance CMOS dynamic random access
memory. The V53C518165A offers Page mode op-
eration with Extended Data Output. The
V53C518165A has symmetric address, 10-bit row
and 10-bit column.
All inputs are TTL compatible. EDO Page Mode
operation allows random access up to 1024 x 16
bits, within a page, with cycle times as short as
20ns.
These features make the V53C518165A ideally
suited for a wide variety of high performance com-
puter systems and peripheral applications.
Device Usage Chart
Operating
Temperature
Range
0
°
C to 70
°
C
–40
°
C to +85
°
C
Package Outline
K
•
•
Access Time (ns)
50
•
•
Power
Std.
•
•
T
•
•
60
•
•
Temperature
Mark
Blank
I
V53C518165A Rev. 1.1 January 1998
1
MOSEL VITELIC
42-Pin Plastic SOJ
PIN CONFIGURATION
Top View
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
VCC
I/O
5
I/O
6
I/O
7
I/O
8
NC
NC
WE
RAS
NC
NC
A0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
V53C518165A
44/50-Pin Plastic TSOP-II
PIN CONFIGURATION
Top View
V
CC
I/O
1
I/O
2
I/O
3
I/O
4
VCC
I/O
5
I/O
6
I/O
7
I/O
8
NC
NC
NC
WE
RAS
NC
NC
A0
A
1
A
2
A
3
V
CC
1
2
3
4
5
6
7
8
9
10
11
15
16
17
18
19
20
21
22
23
24
25
50
49
48
47
46
45
44
43
42
41
40
36
35
34
33
32
31
30
29
28
27
26
511816500-02
V
SS
I/O
16
I/O
15
I/O
14
I/O
13
V
SS
I/O
12
I/O
11
I/O
10
I/O
9
NC
NC
LCAS
UCAS
OE
A
9
A
8
A
7
A
6
A
5
A
4
V
SS
Pin Names
A
0
–A
9
RAS
UCAS
LCAS
WE
OE
I/O
1
–I/O
16
V
CC
V
SS
NC
Row, Column Address Inputs
Row Address Strobe
Column Address Strobe/Upper Byte Control
Column Address Strobe/Lower Byte Control
Write Enable
Output Enable
Data Input, Output
+5V Supply
0V Supply
No Connect
Description
TSOP-II
SOJ
Pkg.
T
K
Pin Count
44/50
42
V53C518165A Rev. 1.1 January 1998
2
MOSEL VITELIC
Absolute Maximum Ratings*
Symbol
V
N
V
DQ
T
BIAS
T
STG
V53C518165A
Parameter
Power Supply Voltage
Input/Output Voltage
Temperature Under Bias
Storage Temperature
Commercial
-1 to +7
-0.5 to min (V
CC
+0.5, 7.0)
-10 to +125
-55 to +125
Extended
-1 to +7
-0.5 to min (V
CC
+0.5, 7.0)
-65 to +135
-65 to +150
Units
V
V
°C
°C
*
Note:
Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
reliability.
Capacitance*
T
A
= 25
°C,
V
CC
= 5 V
±
10%, V
SS
= 0 V, f = 1 MHz
Symbol
C
IN1
C
IN2
C
OUT
Parameter
Address Input
RAS, UCAS, LCAS,
WE, OE
Data Input/Output
Min.
—
—
—
Max.
5
7
7
Unit
pF
pF
pF
*
Note:
Capacitance is sampled and not 100% tested.
Block Diagram
I/O1 I/O2
•••
I/O16
Data In
Buffer
WE
LCAS
UCAS
16
Data Out
Buffer
16
OE
No. 2 Clock
Generator
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
10
Column
Address
Buffers (10)
10
Column
Decoder
Refresh
Controller
Sense Amplifier
I/O Gating
Refresh
Counter (10)
10
Row
Address
Buffers (10)
10
Row
Decoder 1024
Memory Array
1024 x 1024 x 16
1024
x16
16
RAS
No. 1 Clock
Generator
Voltage Down
Generator
VCC
VCC (internal)
316516500-03
V53C518165A Rev. 1.1 January 1998
3
MOSEL VITELIC
DC and Operating Characteristics
(1-2)
T
A
= 0
°C
to 70
°C,
V
CC
= 5 V
±
10%, V
SS
= 0 V, t
T
= 2ns, unless otherwise specified.
Access
Time
Commercial
Min.
–10
V53C518165A
Extended
Min.
–10
Symbol
I
LI
I
LO
Parameter
Input Leakage Current
(any input pin)
Output Leakage Current
(for High-Z State)
Max.
10
Max.
10
Unit Test Conditions
mA
mA
V
SS
£
V
IN
£
V
CC
+
0.5V
V
SS
£
V
OUT
£
V
CC
+
0.5V
RAS, CAS at V
IH
t
RC
= t
RC
(min.)
Notes
1
–10
10
–10
10
1
I
CC1
V
CC
Supply Current,
Operating
V
CC
Supply Current,
TTL Standby
V
CC
Supply Current,
RAS-Only Refresh
V
CC
Supply Current,
EDO Page Mode
Operation
V
CC
Supply Current,
during CAS-before-RAS Refresh
V
CC
Supply Current,
CMOS Standby
50
60
130
115
2
200
180
2
mA
2, 3, 4
I
CC2
I
CC3
mA
RAS, CAS at V
IH
other inputs
³
V
SS
t
RC
= t
RC
(min.)
2, 4
50
60
50
60
50
60
130
115
50
40
130
115
1.0
200
180
90
75
200
180
1.0
mA
I
CC4
mA
Minimum Cycle
2, 3, 4
I
CC5
mA
t
RC
= t
RC
(min.)
2, 4
I
CC6
mA
RAS
³
V
CC
– 0.2 V,
CAS
³
V
CC
– 0.2 V
other input
³
V
SS
CBR cycle with
t
RAS
³
t
RASS (min.)
,
CAS Held Low,
WE = V
CC
-0.2V,
Address and
D
IN
= V
CC
-0.2V or
0.2V
1
I
CC7
Self Refresh (Optional)
250
250
mA
V
CC
V
IL
V
IH
V
OL
V
OH
Power Supply Voltage
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
4.5
–0.5
2.4
5.5
0.8
V
CC
+0.5
0.4
4.5
–0.5
2.4
5.5
0.8
V
CC
+0.5
0.4
V
V
V
V
V
I
OL
= 4.2 mA
I
OH
= –5.0 mA
1
1
1
1
2.4
2.4
V53C518165A Rev. 1.1 January 1998
4
MOSEL VITELIC
T
A
= 0°C to 70°C, V
CC
= 5 V
±
10%, t
T
= 2ns, unless otherwise noted
Limit Values
-50
#
Symbol
Parameter
Min.
Max.
Min.
-60
V53C518165A
AC Characteristics
(5,6)
Max.
Unit
Note
Common Parameters
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
Random read or write cycle time
RAS precharge time
RAS pulse width
CAS pulse width
Row address setup time
Row address hold time
Column address setup time
Column address hold time
RAS to CAS delay time
RAS to column address delay
RAS hold time
CAS hold time
CAS to RAS precharge time
Transition time (rise and fall)
Refresh period
84
30
50
8
0
8
0
8
12
10
13
40
5
1
—
—
—
10k
10k
—
—
—
—
37
25
—
—
—
50
16
104
40
60
10
0
10
0
10
14
12
15
50
5
1
—
—
—
10k
10k
—
—
—
—
45
30
—
—
—
50
16
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
7
Read Cycle
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
t
RAC
t
CAC
t
CAA
t
OAC
t
CAR
t
RCS
t
RCH
t
RRH
t
CLZ
t
OFF
t
OEZ
t
DZC
t
DZO
t
CDD
t
ODD
Access time from RAS
Access time from CAS
Access time from column address
OE access time
Column address to RAS lead time
Read command setup time
Read command hold time
Read command hold time referenced to RAS
CAS to output in low-Z
Output buffer turn-off delay
Output turn-off delay from OE
Data to CAS low delay
Data to OE low delay
CAS high to data delay
OE high to data delay
—
—
—
—
25
0
0
0
0
0
0
0
0
10
10
50
13
25
13
—
—
—
—
—
13
13
—
—
—
—
—
—
—
—
30
0
0
0
0
0
0
0
0
13
13
60
15
30
15
—
—
—
—
—
15
15
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11
8
12
12
13
13
14
14
8, 9
8, 9
8,10
V53C518165A Rev. 1.1 January 1998
5
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