IN74HC240A
O
CTAL
3-S
TATE
I
NVERTING
B
UFFER
/L
INE
D
RIVER
/L
INE
R
ECEIVER
High-Performance Silicon-Gate CMOS
The IN74HC240A is identical in pinout to the LS/ALS240. The
device inputs are compatible with standard CMOS outputs; with
pullup resistors, they are compatible with LS/ALSTTL outputs.
This octal inverting buffer/line driver/line receiver is designed
to be used with 3-state memory address drivers, clock drivers,
and other bus-oriented systems. The device has inverting
outputs and two active-low output enables.
Outputs Directly Interface to CMOS, NMOS, and TTL
Operating Voltage Range: 2.0 to 6.0 V
Low Input Current: 1.0
µA
High Noise Immunity Characteristic of CMOS Devices
•
•
•
•
ORDERING INFORMATION
IN74HC240AN Plastic
IN74HC240ADW SOIC
T
A
= -55° to 125° C for all
packages
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
PIN 20=V
CC
PIN 10 = GND
Inputs
Enable A,
A,B
Enable B
L
L
L
H
H
X
Outputs
YA,YB
H
L
Z
X
=
don’t
Z = high impedance
care
1
IN74HC240A
MAXIMUM RATINGS
*
Symbol
Parameter
Value
Unit
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
mA
±20
I
OUT
DC Output Current, per Pin
mA
±35
I
CC
DC Supply Current, V
CC
and GND Pins
mA
±75
P
D
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg
Storage Temperature
-65 to +150
°C
260
T
L
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
V
CC
DC Supply Voltage (Referenced to GND)
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to
GND)
T
A
Operating Temperature, All Package Types
t
r
, t
f
Input Rise and Fall Time
(Figure V
CC
=2.0 V
1)
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, V
IN
and
V
OUT
should be constrained to the range GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
V
CC
). Unused outputs must be left open.
2
IN74HC240A
DC ELECTRICAL CHARACTERISTICS(Voltages
Referenced to GND)
Guaranteed Limit
V
CC
Symbol Parameter
Test Conditions
V
25
°C
to
≤85 ≤125
-55°C
°C
°C
1.5
1.5
V
OUT
=0.1 V
1.5
V
IH
Minimum High-
2.0
3.15 3.15
3.15
Level Input
4.5
I
OUT
≤
20
µA
4.2
4.2
4.2
Voltage
6.0
0.5
0.5
V
OUT
= V
CC
-0.1 V
0.5
V
IL
Maximum Low -
2.0
1.35 1.35
1.35
Level Input
4.5
I
OUT
≤
20
µA
1.8
1.8
1.8
Voltage
6.0
1.9
1.9
V
IN
= V
IL
1.9
V
OH
Minimum High-
2.0
4.4
4.4
4.4
Level Output
4.5
I
OUT
≤
20
µA
5.9
5.9
5.9
Voltage
6.0
V
IN
=V
IL
3.7
3.84
3.98
4.5
I
OUT
≤
6.0 mA
5.2
5.34
5.48
6.0
I
OUT
≤
7.8 mA
0.1
0.1
V
IN
=V
IH
0.1
V
OL
Maximum Low-
2.0
0.1
0.1
0.1
Level Output
4.5
I
OUT
≤
20
µA
0.1
0.1
0.1
Voltage
6.0
V
IN
= V
IH
0.4
0.33
0.26
4.5
I
OUT
≤
6.0 mA
0.4
0.33
0.26
6.0
I
OUT
≤7.8
mA
I
IN
Maximum Input
V
IN
=V
CC
or GND
6.0
±0.1
±1.0 ±1.0
Leakage Current
Output in High-
I
OZ
Maximum three
6.0
±0.5
±5.0 ±10.
Impedance State
State Leakage
0
V
IN
= V
IL
or V
IH
Current
V
OUT
=V
CC
or GND
V
IN
=V
CC
or GND
I
CC
Maximum
6.0
4.0
40
160
Quiescent Supply I
OUT
=0µA
Current
(per Package)
Unit
V
V
V
V
µA
µA
µA
3
IN74HC240A
AC ELECTRICAL CHARACTERISTICS(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
V
CC
Symbol
Parameter
V
25
°C ≤85°C ≤125
to
°C
-55°C
120
100
80
t
PLH
,
Maximum Propagation Delay, A to YA or 2.0
24
20
16
t
PHL
B to YB (Figures 1 and 3)
4.5
20
17
14
6.0
165
140
110
t
PLZ
,
Maximum Propagation Delay, Output 2.0
33
28
22
t
PHZ
Enable to YA or YB (Figures 2 and 4)
4.5
28
24
19
6.0
165
140
110
t
PZH
,
Maximum Propagation Delay, Output 2.0
33
28
22
t
PZL
Enable to YA or YB (Figures 2 and 4)
4.5
28
24
19
6.0
90
75
60
t
TLH
, t
THL
Maximum Output Transition Time, Any 2.0
18
15
12
4.5
Output
15
13
10
6.0
(Figures 1 and 3)
C
IN
Maximum Input Capacitance
-
10
10
10
-
15
15
15
C
OUT
Maximum
Three-State
Output
Capacitance
(Output in High-Impedance State)
Power Dissipation Capacitance (Per
Transceiver Channel)
Used to determine the no-load dynamic
power
consumption:
2
P
D
=C
PD
V
CC
f+I
CC
V
CC
Typical @25°C,V
CC
=5.0 V
32
pF
Unit
ns
ns
ns
ns
pF
pF
C
PD
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
4
IN74HC240A
Figure 3. Test Circuit
Figure 4. Test Circuit
EXPANDED LOGIC DIAGRAM
(1/8 of the Device)
5
Electronics Design Contest
京公网安备 11010802033920号
EEWORLD
