TECHNICAL DATA
IN74HC21A
Dual 4-Input AND Gate
The IN74HC21A is high-speed Si-gate CMOS device and is pin
compatible with pullup resistors with low power Schottky TTL
(LSTTL). The device provide the Dual 4-input AND function.
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 2.0 to 6.0 V
•
Low Input Current: 1.0
µA
•
High Noise Immunity Characteristic of CMOS Devices
ORDERING INFORMATION
IN74HC21AN
Plastic
IN74HC21AD
SOIC
IZ74HC21A Chip
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
A1
1
2
3
C1
D1
4
5
6
7
14
13
12
11
10
9
8
B2
A2
Y2
V CC
D2
C2
A1
B1
Y1
C1
B1
A2
B2
Y2
C2
D2
A
L
X
PIN 14 =V
CC
PIN 7 = GND
X
X
H
X = don’t care
B
X
L
X
X
H
Y1
GND
FUNCTION TABLE
Inputs
Ñ
X
X
L
X
H
D
X
X
X
L
H
Output
Y
L
L
L
L
H
INTEGRAL
1
IN74HC21A
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
I
OUT
I
CC
P
D
Tstg
T
L
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
DC Output Current, per Pin
DC Supply Current, V
CC
and GND Pins
Power Dissipation in Still Air, Plastic DIP**
SOIC Package**
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +7.0
-1.5 to V
CC
+1.5
-0.5 to V
CC
+0.5
±20
±25
±50
750
500
-65 to +150
260
Unit
V
V
V
mA
mA
mA
mW
°C
°C
*Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
**Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
t
r
, t
f
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Input Rise and Fall Time (Figure 1)
V
CC
=2.0 V
V
CC
=4.5 V
V
CC
=6.0 V
Min
2.0
0
-55
0
0
0
Max
6.0
V
CC
+125
1000
500
400
Unit
V
V
°C
ns
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages
to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range GND≤(V
IN
or
V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
). Unused
outputs must be left open.
INTEGRAL
2
IN74HC21A
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF,Input t
r
=t
f
=6.0 ns)
V
CC
Symbol
t
PHL
, t
PLH
Parameter
Maximum Propagation Delay (Figure 1)
V
2.0
4.5
6.0
2.0
4.5
6.0
5.0
Guaranteed Limit
25
°C
to
-55°C
110
22
19
75
15
13
10
≤85°C
140
28
24
95
19
16
10
≤125°C
165
33
28
110
22
19
10
Unit
ns
t
THL
, t
TLH
Maximum Output Transition Time
(Figure 1)
Maximum Input Capacitance
ns
C
IN
pF
Power Dissipation Capacitance (Per Gate)
C
PD
Used to determine the no-load dynamic power
consumption:
P
D
=C
PD
V
CC2
f+I
CC
V
CC
T
A
=25°C,V
CC
=5.0 V
50
pF
t
LH
0.9
0.9
V
2
t
HL
V
1
Input
0.1
V
2
0.1
GND
V
CC
t
PLH
0.9
t
PHL
0.9
V
2
0.1
Output
V
2
0.1
0V
t
TLH
V
1
= 0.5 V
CC
t
THL
Figure 1. Switching Waveforms
V
CC
V
I
PULSE
GENERATOR
R
T
DEVICE
UNDER
TEST
V
O
Termination resistance R
T
– should
be equal to Z
OUT
of pulse
generators
C
L
50 pF
Figure 2. Test Circuit
INTEGRAL
4
51mcu
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