TECHNICAL DATA
IW4093B
Quad 2-Input NAND Schmitt Triggers
High-Voltage Silicon-Gate CMOS
The IW4093B consists of four Schmitt-trigger circuits. Each circuit
functions as a two-input NAND gate with Schmitt-trigger action on
both inputs. The gate switches at different points for positive- and
negative- going signals. The difference between the positive voltage
(V
P
) and the negative voltage (V
N
) is defined as hysteresis voltage (V
H
)
(see Fig.1).
•
Operating Voltage Range: 3.0 to 18 V
•
Maximum input current of 1
µA
at 18 V over full package-
temperature range; 100 nA at 18 V and 25°C
•
Noise margin (over full package temperature range):
1.0 V min @ 5.0 V supply
2.0 V min @ 10.0 V supply
2.5 V min @ 15.0 V supply
ORDERING INFORMATION
IW4093BN Plastic
IW4093BD SOIC
T
A
= -55° to 125° C for all packages
LOGIC DIAGRAM
PIN ASSIGNMENT
FUNCTION TABLE
Inputs
A
L
PIN 14 =V
CC
PIN 7 = GND
L
H
H
B
L
H
L
H
Output
Y
H
H
H
L
142
IW4093B
MAXIMUM RATINGS
*
Symbol
V
CC
V
IN
V
OUT
I
IN
P
D
P
D
Tstg
T
L
*
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
Power Dissipation in Still Air, Plastic DIP+
SOIC Package+
Power Dissipation per Output Transistor
Storage Temperature
Lead Temperature, 1 mm from Case for 10 Seconds
(Plastic DIP or SOIC Package)
Value
-0.5 to +20
-0.5 to V
CC
+0.5
-0.5 to V
CC
+0.5
±10
750
500
100
-65 to +150
260
Unit
V
V
V
mA
mW
mW
°C
°C
Maximum Ratings are those values beyond which damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
IN
, V
OUT
T
A
Parameter
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
Min
3.0
0
-55
Max
18
V
CC
+125
Unit
V
V
°C
This device contains protection circuitry to guard against damage due to high static voltages or electric
fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated
voltages to this high-impedance circuit. For proper operation, V
IN
and V
OUT
should be constrained to the range
GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V
CC
).
Unused outputs must be left open.
143
IW4093B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND)
V
CC
Symbol
V
T
+min
Parameter
Minimum Positive-
Going Input
Threshold Voltage
Test Conditions
Input on terminals A or B;
other inputs to V
CC
Input on terminals A and B;
other inputs to V
CC
V
T
+max
Maximum Positive-
Going Input
Threshold Voltage
Input on terminals A or B;
other inputs to V
CC
Input on terminals A and B;
other inputs to V
CC
V
T
-min
Minimum Negative-
Going Input
Threshold Voltage
Input on terminals A or B;
other inputs to V
CC
Input on terminals A and B;
other inputs to V
CC
V
T
-max
Maximum Negative-
Going Input
Threshold Voltage
Input on terminals A or B;
other inputs to V
CC
Input on terminals A and B;
other inputs to V
CC
V
H
min
Note
Minimum Hysteresis
Voltage
Input on terminals A or B;
other inputs to V
CC
Input on terminals A and B;
other inputs to V
CC
V
H
max
Note
Maximum Hysteresis
Voltage
Input on terminals A or B;
other inputs to V
CC
Input on terminals A and B;
other inputs to V
CC
I
IN
Maximum Input
Leakage Current
V
IN
= GND or V
CC
V
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
5.0
10
15
18
Guaranteed Limit
≥-55°C
2.2
4.6
6.8
2.6
5.6
6.3
3.6
7.1
10.8
4
8.2
12.7
0.9
2.5
4
1.4
3.4
4.8
2.8
5.2
7.4
3.2
6.6
9.6
0.3
1.2
1.6
0.3
1.2
1.6
1.6
3.4
5
1.6
3.4
5
±0.1
25°C
2.2
4.6
6.8
2.6
5.6
6.3
3.6
7.1
10.8
4
8.2
12.7
0.9
2.5
4
1.4
3.4
4.8
2.8
5.2
7.4
3.2
6.6
9.6
0.3
1.2
1.6
0.3
1.2
1.6
1.6
3.4
5
1.6
3.4
5
±0.1
≤125
°C
2.2
4.6
6.8
2.6
5.6
6.3
3.6
7.1
10.8
4
8.2
12.7
0.9
2.5
4
1.4
3.4
4.8
2.8
5.2
7.4
3.2
6.6
9.6
0.3
1.2
1.6
0.3
1.2
1.6
1.6
3.4
5
1.6
3.4
5
±1.0
µA
V
V
V
V
V
Unit
V
144
IW4093B
DC ELECTRICAL CHARACTERISTICS
(Voltages Referenced to GND) - continued
V
CC
Symbol
I
CC
Parameter
Maximum Quiescent
Supply Current
(per Package)
Test Conditions
V
IN
= GND or V
CC
V
5.0
10
15
20
5.0
10
15
5.0
5.0
10
15
5.0
10
15
5.0
10
15
Guaranteed Limit
≥-55°C
1
2
4
20
0.64
1.6
4.2
-2.0
-0.64
-1.6
-4.2
4.95
9.95
14.95
0.05
0.05
0.05
25°C
1
2
4
20
0.51
1.3
3.4
-1.6
-0.51
-1.3
-3.4
4.95
9.95
14.95
0.05
0.05
0.05
≤125
°C
30
60
120
600
0.36
0.9
2.4
mA
-1.15
-0.36
-0.9
-2.4
4.95
9.95
14.95
0.05
0.05
0.05
V
Unit
µA
I
OL
Minimum Output Low V
IN
= GND or V
CC
(Sink) Current
U
OL
=0.4 V
U
OL
=0.5 V
U
OL
=1.5 V
Minimum Output
V
IN
= GND or V
CC
High (Source) Current U
OH
=2.5 V
U
OH
=4.6 V
U
OH
=9.5 V
U
OH
=13.5 V
Minimum High-Level
Output Voltage
Maximum Low-Level
Output Voltage
V
IN
=GND or V
CC
mA
I
OH
V
OH
V
OL
V
IN
= V
CC
V
Note. V
H
min>(V
T+
min)-(V
T-
max); V
H
max=(V
T+
max)+(V
T-
min).
AC ELECTRICAL CHARACTERISTICS
(C
L
=50pF, R
L
=200kΩ, Input t
r
=t
f
=20 ns)
V
CC
Symbol
t
PLH
, t
PHL
Parameter
Maximum Propagation Delay, Input A or B to
Output Y (Figure 2)
Maximum Output Transition Time, Any Output
(Figure 2)
Maximum Input Capacitance
V
5.0
10
15
5.0
10
15
-
380
180
130
200
100
80
Guaranteed Limit
≥-55°C
25°C
380
180
130
200
100
80
7.5
≤125°C
760
360
260
400
200
160
Unit
ns
t
TLH
, t
THL
ns
C
IN
pF
145
IW4093B
a) Definition of V
T
+, V
T
-, V
H
c) Test setup
b) Transfer characteristic of 1 of 4 gates
Figure 1. Hysteresis definition, characteristic, and test setup
Figure 2. Switching Waveforms
EXPANDED LOGIC DIAGRAM
(1/4 of the Device)
146
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
