tm
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•
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TE
CH
T436416D
SDRAM
FEATURES
Fast access time from clock: 4.5/5/5.4 ns
Fast clock rate: 200/166/143 MHz
Fully synchronous operation
Internal pipelined architecture
1M word x 16-bit x 4-bank
Programmable Mode registers
- CAS# Latency: 2, or 3
- Burst Length: 1, 2, 4, 8, or full page
- Burst Type: interleaved or linear burst
- Burst stop function
•
Auto Refresh and Self Refresh
•
4096 refresh cycles/64ms
•
CKE power down mode
•
Single +3.3V
±
0.3V power supply
•
Interface: LVTTL
•
54-pin 400 mil plastic TSOP II package
•
60-Ball, 6.4 mm x 10.1 mm TFBGA package
4M x 16 SDRAM
1M x 16bit x 4Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T436416D SDRAM is a high-speed CMOS
synchronous DRAM containing 64 Mbits. It is internally
configured as 4 Banks of 1M word x 16 DRAM with a
synchronous interface (all signals are registered on the
positive edge of the clock signal, CLK). Read and write
accesses to the SDRAM are burst oriented; accesses
start at a selected location and continue for a
programmed number of locations in a programmed
sequence. Accesses begin with the registration of a
BankActivate command which is then followed by a
Read or Write command.
The T436416D provides for programmable Read
or Write burst lengths of 1, 2, 4, 8, or full page, with a
burst termination option. An auto precharge function
may be enabled to provide a self-timed row precharge
that is initiated at the end of the burst sequence. The
refresh functions, either Auto or Self Refresh are easy to
use.
By having a programmable mode register, the
system can choose the most suitable modes to maximize
its performance. These devices are well suited for
applications requiring high memory bandwidth and
particularly well suited to high performance PC
applications.
Key Specifications
T436416D
-
5/6/7
5/6/7 ns
4.5/5/5.4/ ns
35/42/45 ns
50/60/63 ns
t
CK3
t
AC3
t
RAS
t
RC
Clock Cycle time(min.)
Access time from CLK(max.)
Row Active time(min.)
Row Cycle time(min.)
ORDERING INFORMATION
Part Number
T436416D-5S/-5C
T436416D-5SG/-5CG
T436416D-6S/-6C
T436416D-6SG/-6CG
T436416D-7S/-7C
Frequency
200MHz
200MHz
166MHz
166MHz
143MHz
Package
TSOP II / TFBGA
TSOP II / TFBGA
TSOP II / TFBGA
TSOP II / TFBGA
TSOP II / TFBGA
TSOP II / TFBGA
T436416D-7SG/-7CG 143MHz
S : indicates TSOPII Package,
C : indicates TFBGA Package,
G : indicates Pb Free Package
TM Technology Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
1
A
VSS
B
DQ14
TE
CH
T436416D
PIN ARRANGEMENT (Top
View)
TFBGA Top View
2
3
4
5
6
7
DQ15
DQ0
VDD
TOSPII Top View
V
DD
DQ0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
5 4 P IN T S O P ( II)
( 4 0 0 m il x 8 7 5 m il)
( 0 .8 m m P IN P IT C H )
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V ss
D Q 15
V
SSQ
D Q 14
D Q 13
V
DDQ
D Q 12
D Q 11
V
SSQ
D Q 10
DQ9
V
DDQ
DQ8
V ss
N .C /R F U
UDQM
C LK
CKE
N .C
A 11
A9
A8
A7
A6
A5
A4
V ss
VSSQ
VDDQ
DQ1
V
DDQ
DQ1
C
DQ13 VDDQ
VSSQ
DQ2
DQ2
V
SSQ
D
DQ12
DQ11
DQ4
DQ3
DQ3
DQ4
E
DQ10 VSSQ
VDDQ
DQ5
V
DDQ
DQ5
F
DQ9
VDDQ
VSSQ
DQ6
DQ6
V
SSQ
DQ7
G
DQ8
NC
NC
DQ7
H
NC
NC
NC
NC
V
DD
LD Q M
J
NC
UDQM
LDQM
WE#
WE
CAS
K
NC
CLK
RAS#
CAS#
RAS
CS
L
CKE
NC
NC
CS#
BA0
BA1
M
A11
A9
BA1
B
A0
A 1 0 /A P
A0
A1
N
A8
A7
A0
A10
P
A6
A5
A2
A1
A2
A3
R
VSS
A4
A3
VDD
V
DD
TM Technology Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
TE
CH
T436416D
BLOCK DIAGRAM
I/O Control
LW E
Bank Select
D ata Input R egister
LD Q M
1M x 16
1M x 16
1M x 16
1M x 16
Row Decoder
Row Buffeer
Refresh Counter
Sense AM P
Output Buffer
D Qi
Address Register
C LK
A DD
LCBR
LRAS
Col. Buffer
C olum n D ecoder
Latency & Burst Length
LC K E
LR A S
LC BR
LW E
LC A S
Tim ing Register
Program m ing R egister
LW C BR
LD Q M
C LK
C KE
CS
R AS
C AS
WE
L(U)D QM
TM Technology Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
Symbol
CLK
CKE
TE
CH
Type
Input
Input
Description
T436416D
Pin Descriptions
(
Table 1. Pin Details of T436416D)
Clock:
CLK is driven by the system clock. All SDRAM input signals are sampled on the positive edge
of CLK. CLK also increments the internal burst counter and controls the output registers.
Clock Enable:
CKE activates(HIGH) and deactivates(LOW) the CLK signal. If CKE goes low
synchronously with clock(set-up and hold time same as other inputs), the internal clock is suspended
from the next clock cycle and the state of output and burst address is frozen as long as the CKE
remains low. When all banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes. CKE is synchronous except after the device enters Power Down and
Self Refresh modes, where CKE becomes asynchronous until exiting the same mode. The input
buffers, including CLK, are disabled during Power Down and Self Refresh modes, providing low
standby power.
Bank Select:
BA0,BA1 input select the bank for operation.
BA1
BA0
0
0
0
1
1
0
1
1
Select Bank
BANK #A
BANK #B
BANK #C
BANK #D
BA0,BA1
Input
A0-A11
Input
Address Inputs:
A0-A11 are sampled during the BankActivate command (row address A0-A11) and
Read/Write command (column address A0-A7 with A10 defining Auto Precharge) to select one
location out of the 1M available in the respective bank. During a Precharge command, A10 is sampled
to determine if all banks are to be precharged (A10 = HIGH). The address inputs also provide the op-
code during a Mode Register Set command.
Chip Select:
CS# enables (sampled LOW) and disables (sampled HIGH) the command decoder. All
commands are masked when CS# is sampled HIGH. CS# provides for external bank selection on
systems with multiple banks. It is considered part of the command code.
Row Address Strobe:
The RAS# signal defines the operation commands in conjunction with the
CAS# and WE# signals and is latched at the positive edges of CLK. When RAS# and CS# are asserted
"LOW" and CAS# is asserted "HIGH," either the BankActivate command or the Precharge command
is selected by the WE# signal. When the WE# is asserted "HIGH," the BankActivate command is
selected and the bank designated by BS is turned on to the active state. When the WE# is asserted
"LOW," the Precharge command is selected and the bank designated by BS is switched to the idle state
after the precharge operation.
Column Address Strobe:
The CAS# signal defines the operation commands in conjunction with the
RAS# and WE# signals and is latched at the positive edges of CLK. When RAS# is held "HIGH" and
CS# is asserted "LOW," the column access is started by asserting CAS# "LOW." Then, the Read or
Write command is selected by asserting WE# "LOW" or "HIGH."
Write Enable:
The WE# signal defines the operation commands in conjunction with the RAS# and
CAS# signals and is latched at the positive edges of CLK. The WE# input is used to select the
BankActivate or Precharge command and Read or Write command.
Data Input/Output Mask:
Controls output buffers in read mode and masks Input data in write mode.
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
LDQM,
UDQM
Input
DQ0-DQ15 Input / Output
Data I/O:
The DQ0-15 input and output data are synchronized with the positive edges of CLK. The
I/Os are maskable during Reads and Writes.
NC/RFU
V
DDQ
V
SSQ
V
DD
V
SS
-
Supply
Supply
Supply
Supply
No Connect:
These pins should be left unconnected.
DQ Power:
Provide isolated power to DQs for improved noise immunity. ( 3.3V± 0.3V )
DQ Ground:
Provide isolated ground to DQs for improved noise immunity.( 0 V )
Power Supply:
+3.3V
±
0.3V
Ground
TM Technology Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
tm
TE
CH
T436416D
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK. Table 2 shows
the truth table for the operation commands.
Table 2. Truth Table (Note (1), (2) )
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and AutoPrecharge
Read
Read and Autoprecharge
Mode Register Set
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
State
Idle
(3)
Any
Any
Active
(3)
Active
(3)
Active
(3)
Active
(3)
Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
CKE
n-1
CKE
n
DQM BA
0,1
A
10
A
0-9,11
CS# RAS# CAS# WE#
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
L
L
H
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
X
X
X
V
V
X
V
V
V
V
Row address
L
H
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
Column
address (A0
~ A7)
Column
address (A0
~ A7)
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
H
L
L
L
L
H
H
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
OP code
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Entry
Power Down Mode Entry
Active
Any
(5)
Active
Any
(PowerDown)
Clock Suspend Mode Exit
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
Active
Note:
Active
H
X
H
X
X
X
X
1. V=Valid X=Don't Care L=Low level H=High level
2. CKE
n
signal is input level when commands are provided.
CKE
n-1
signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1, 2, 4, 8, and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle, device state is clock suspend mode.
TM Technology Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: FEB. 2007
Revision: A
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