IW4042BN datasheet, PDF - EEWORLD Datasheet

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IW4042BN: Descriptionquad clocked ?D? latch high-voltage silicon-gate cmos; File Size189KB，6 Pages; ManufacturerIK Semicon; Websitehttp://www.iksemi.com/en/index.html

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IW4042BN Overview

quad clocked ?D? latch high-voltage silicon-gate cmos

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TECHNICAL DATA

IW4042B

Quad Clocked «D» Latch

High-Voltage Silicon-Gate CMOS

IW4042B types contain four latch circuits, each strobed by a common

clock. Complementary buffered outputs are available from each circuit.

The impedance of the n- and p-channel output devices is balanced and all

outputs are electrically identical. Information present at the data input is

transferred to outputs Q and Q during the CLOCK level which is

programmed by the POLARITY input. For POLARITY = 0 the transfer

occurs during the 0 CLOCK level and for POLARITY = 1 the transfer

occurs during the 1 CLOCK level. The outputs follow the data input

providing the CLOCK and POLARITY levels defined above are present.

When a CLOCK transition occurs (positive for POLARITY = 0 and

negative for POLARTY = 1) the information present at the input during

the CLOCK transition is retained at the outputs until an opposite CLOCK

transition occurs.

The IW4042B types are supplied in 16-lead hermetic dual-in-line

ceramic packages (D and F suffixes); 16-lead dual-in-line plastic package

(E suffix), and in chip form (H suffix).

•

Operating Voltage Range: 3.0 to 18 V

•

Maximum input current of 1

μA

at 18 V over full package-

temperature range; 100 nA at 18 V and 25°C

•

Noise margin (over full package temperature range):

1.0 V min @ 5.0 V supply

2.0 V min @ 10.0 V supply

2.5 V min @ 15.0 V supply

ORDERING INFORMATION

IW4042BN Plastic

IW4042BD SOIC

= -55° to 125° C for all packages

PIN ASSIGNMENT

LOGIC DIAGRAM

FUNCTION TABLE

Inputs

Clock

PIN 16 =V

PIN 8 = GND

Polarity

Outputs

Latch

Rev. 00

IW4042BN Related Products

	IW4042BN	IW4042B	IW4042BD
Description	quad clocked ?D? latch high-voltage silicon-gate cmos	quad clocked ?D? latch high-voltage silicon-gate cmos	quad clocked ?D? latch high-voltage silicon-gate cmos

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