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P701-10DC: DescriptionLow EMI Spread Spectrum Multiplier IC (in Die or Package); File Size231KB，8 Pages; ManufacturerPLL (PhaseLink Corporation)

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P701-10DC Overview

Low EMI Spread Spectrum Multiplier IC (in Die or Package)

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PLL701-10

Low EMI Spread Spectrum Multiplier IC (in Die or Package)

FEATURES

•

Spread Spectrum Clock Generator/Multiplier with

output selectable from 1x to 8x.

13MHz to 240MHz output with output enable.

13MHz to 30 MHz reference input frequency

accepted from crystal or external clock signal.

Reduced EMI from Spread Spectrum Modulation,

with selectable modulation amplitude for Center

Spread, Down Spread or Asymmetric Spread.

TTL/CMOS compatible outputs.

3.3V Operating Voltage.

150 ps maximum cycle-to-cycle jitter.

Available in 16-Pin 150mil SSOP or DIE.

PACKAGE PIN CONFIGURATION

XIN/FIN

XOUT/SD0*^

M2^

M1^

M0^

SC0^

SC1^

SC2^

GND

AVDD

REF/SD1*^

VDD

SC3^

OE^

FOUT

GND

PLL 701-10

XIN/FIN = 10 ~ 30 MHz

DESCRIPTION

The PLL701-10 is a low EMI Clock Generator and

Multiplier for high-speed digital systems. It uses

Spread Spectrum Technology (SST) and permits

different levels of EMI reduction by selecting the

amplitude of the applied SST. The SST feature can

be turned off. An output enable input is also used.

The chip operates with input frequencies ranging from

13 to 30 MHz and provides 1x to 8x at its output.

DIE PAD CONFIGURATION

69 mil

AVDD

GND

XIN

1700, 2540

AVDD

XOUT/SD0*^

(Optional)

GNDOSC

C501A

A0404

-04A

AVDD

REF/SD1*^

VDD

VDD (optional)

SC3^

OUTPUT CLOCK (FOUT) SELECTION

FIN/XIN

(MHz)

13 ~ 28

14 ~ 30

13 ~ 28

20 ~ 30

17 ~ 30

15 ~ 30

13 ~ 28

Multiplier

FOUT

(MHz)

13 ~ 28

26 ~ 56

42 ~ 90

52 ~ 112

100 ~ 150

102 ~ 180

105 ~ 210

104 ~ 224

104 mil

M2^

M1^

M0^

OE^

SC0^

SC1^

4 5

FOUT

GNDBUF

SC2^

GND

BLOCK DIAGRAM

XIN

XOUT

M(0:2)

SD(0:1)

SC(0:3)

XTAL

OSC

PLL

SST

Control

Logic

FOUT

Note:

^: Internal pull-up resistor (120kΩ for SD0, 30 kΩ for SC0-

SC2, SD1, M0-M2 and OE). The internal pull-up resistor

results in a default high value when no pull-down resistor is

connected to this pin.

*: SD0 and SD1 are latched upon power-up.

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 09/20/04 Page 1

PLL701-10

Low EMI Spread Spectrum Multiplier IC (in Die or Package)

FUNCTIONAL DESCRIPTION

Selectable spread spectrum and modulation rates

The PLL701-10 provides selectable multiplier factors (1x to 8X), selectable spread spectrum modulation, as well as

selectable modulation rate. Selection is made by connecting specific input pins to a logical “zero” or “one”. Pins 6

(SC0), 7 (SC1), 8 (SC2) and 12 (SC3) are used as inputs to select the spread spectrum modulation as shown on

the spread spectrum selection table (page 2). Pins 3 (M2), 4 (M1), 5 (M0) are used as inputs to select the output

frequency as shown on the output clock selection table (page 1). Pin 11 is the output enable pin, that tri-states all

outputs when low (logical “zero”).

In order to reduce the number of pins on the chip, the PLL701-10 uses pin 2 and 14 (XOUT/SD0 and REF/SD1) as

a bi-directional pin. The pins serve as modulation rate selector inputs (SD0 and SD1) upon power-up (see

modulation rate table on page 1), and as XOUT crystal connection (pin 2), and REF output signal (pin 14) as soon

as the inputs have been latched.

Connecting a selection pin to a logical “one”

All selection pins have an internal pull-up resistor (30kΩ for pins 3, 4, 5, 6, 7, 8, 11, 12, 14 and 120kΩ for pin 2).

This internal pull-up resistor will pull the input value to a logical “one” (pull-up) by default, i.e. when no resistive

load is connected between the pin and GND. No external pull-up resistor is therefore required for connecting a

logical “one” upon power-up.

Connecting a selection pin to a logical “zero”

For an input only pin, i.e. all input pins except XOUT/SD0 (pin 2) and REF/SD1 (pin 14), the pin simply needs to be

grounded to pull the input down to a logical “zero”. Connecting the bi-directional pins (SD0 and SD1) to a logical

“zero” will however require the use of an external loading resistor between the pin and GND that has to be

sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical

“zero”). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor

should however be kept as large as possible. In general, it is recommended to use an external resistor of around

Rup/4 (e.g. 27kΩ for pin 2 and 4.7kΩ for pin 14, see Application Diagram).

APPLICATION DIAGRAM FOR OUTPUT AND MODULATION SELECTION

Internal to chip

VDD

External Circuitry

Power Up

Reset

XIN

Bi-directional pin

Clock Load

SD0 or

SC0~SC2

Latch

Jumper

options

NOTE:

Rup=120kΩ for SD0 (Pin2); and Rup=30kΩ for SD1(Pin 14). R starts from 1 to 0 while RB starts from 0 to 1.

47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991

www.phaselink.com

Rev 09/20/04 Page 4

P701-10DC Related Products

	P701-10DC	P701-10XC	PLL701-10XC	PLL701-10XC-R	PLL701-10XI
Description	Low EMI Spread Spectrum Multiplier IC (in Die or Package)	Low EMI Spread Spectrum Multiplier IC (in Die or Package)	Low EMI Spread Spectrum Multiplier IC (in Die or Package)	Low EMI Spread Spectrum Multiplier IC (in Die or Package)	Low EMI Spread Spectrum Multiplier IC (in Die or Package)

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