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P701-10XC

Description
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
File Size231KB,8 Pages
ManufacturerPLL (PhaseLink Corporation)
Download Datasheet Compare View All

P701-10XC Overview

Low EMI Spread Spectrum Multiplier IC (in Die or Package)

PLL701-10
Low EMI Spread Spectrum Multiplier IC (in Die or Package)
FEATURES
Spread Spectrum Clock Generator/Multiplier with
output selectable from 1x to 8x.
13MHz to 240MHz output with output enable.
13MHz to 30 MHz reference input frequency
accepted from crystal or external clock signal.
Reduced EMI from Spread Spectrum Modulation,
with selectable modulation amplitude for Center
Spread, Down Spread or Asymmetric Spread.
TTL/CMOS compatible outputs.
3.3V Operating Voltage.
150 ps maximum cycle-to-cycle jitter.
Available in 16-Pin 150mil SSOP or DIE.
PACKAGE PIN CONFIGURATION
XIN/FIN
XOUT/SD0*^
M2^
M1^
M0^
SC0^
SC1^
SC2^
1
2
16
15
GND
AVDD
REF/SD1*^
VDD
SC3^
OE^
FOUT
GND
PLL 701-10
3
4
5
6
7
8
14
13
12
11
10
9
XIN/FIN = 10 ~ 30 MHz
DESCRIPTION
The PLL701-10 is a low EMI Clock Generator and
Multiplier for high-speed digital systems. It uses
Spread Spectrum Technology (SST) and permits
different levels of EMI reduction by selecting the
amplitude of the applied SST. The SST feature can
be turned off. An output enable input is also used.
The chip operates with input frequencies ranging from
13 to 30 MHz and provides 1x to 8x at its output.
DIE PAD CONFIGURATION
69 mil
AVDD
GND
GND
XIN
1700, 2540
18
AVDD
XOUT/SD0*^
23
22
21
(Optional)
20
(Optional)
19
GNDOSC
25
C501A
A0404
-04A
17
16
15
14
13
12
AVDD
REF/SD1*^
VDD
VDD (optional)
VDD (optional)
SC3^
OUTPUT CLOCK (FOUT) SELECTION
M2
0
0
0
0
1
1
1
1
M1
0
0
1
1
0
0
1
1
M0
0
1
0
1
0
1
0
1
FIN/XIN
(MHz)
13 ~ 28
13 ~ 28
14 ~ 30
13 ~ 28
20 ~ 30
17 ~ 30
15 ~ 30
13 ~ 28
Multiplier
X1
X2
X3
X4
X5
X6
X7
X8
FOUT
(MHz)
13 ~ 28
26 ~ 56
42 ~ 90
52 ~ 112
100 ~ 150
102 ~ 180
105 ~ 210
104 ~ 224
104 mil
M2^
M1^
M0^
28
29
30
10
OE^
SC0^
SC1^
34
35
1
4 5
6
8
7
FOUT
GNDBUF
SC2^
GND
GND
GND
Y
X
BLOCK DIAGRAM
XIN
XOUT
M(0:2)
SD(0:1)
SC(0:3)
OE
XTAL
OSC
PLL
SST
Control
Logic
FOUT
Note:
^: Internal pull-up resistor (120kΩ for SD0, 30 kΩ for SC0-
SC2, SD1, M0-M2 and OE). The internal pull-up resistor
results in a default high value when no pull-down resistor is
connected to this pin.
*: SD0 and SD1 are latched upon power-up.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991
www.phaselink.com
Rev 09/20/04 Page 1

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