IN74HCT109
D
UAL
J-K F
LIP
-F
LOP
WITH SET AND
R
ESET
High-Performance Silicon-Gate CMOS
The IN74HCT109 is identical in pinout to the LS/ALS109. The
IN74HCT109 may be used as a level converter for interfacing
TTL or NMOS outputs to High Speed CMOS inputs.
This device consists of two J-
K
flip-flops with individual set,
reset, and clock inputs. Changes at the inputs are reflected at the
outputs with the next low-to-high transition of the clock. Both Q to
Q
outputs are available from each flip-flop.
•
TTL/NMOS Compatible Input Levels
•
Outputs Directly Interface to CMOS, NMOS, and TTL
•
Operating Voltage Range: 4.5 to 5.5 V
•
Low Input Current: 1.0
µA
ORDERING INFORMATION
IN74HCT109N Plastic
IN74HCT109D SOIC
T
A
= -55° to 125° C for all
packages.
PIN ASSIGNMENT
LOGIC DIAGRAM
FUNCTION TABLE
Set
L
H
L
H
H
H
H
H
Inputs
Reset Clock
H
L
L
H
H
H
H
H
X
X
X
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Output
Q
Q
H
L
L
H
*
H
H
*
L
H
Toggle
No
Change
H
L
No
Change
PIN 16=V
CC
PIN 8 = GND
L
X = Don’t care
*
Both outputs will remain high as long as
Set and Reset are low., but the output
states are unpredictable if Set and Reset
go high simultaneously.
1
IN74HCT109
MAXIMUM RATINGS
*
Symb
Parameter
Value
Unit
ol
V
CC
DC Supply Voltage (Referenced to GND)
-0.5 to +7.0
V
V
IN
DC Input Voltage (Referenced to GND)
-1.5 to V
CC
+1.5
V
V
OUT
DC Output Voltage (Referenced to GND)
-0.5 to V
CC
+0.5
V
I
IN
DC Input Current, per Pin
mA
±20
I
OUT
DC Output Current, per Pin
mA
±25
I
CC
DC Supply Current, V
CC
and GND Pins
mA
±50
P
D
Power Dissipation in Still Air, Plastic DIP+
750
mW
SOIC Package+
500
Tstg Storage Temperature
-65 to +150
°C
260
T
L
Lead Temperature, 1 mm from Case for 10
°C
Seconds
(Plastic DIP or SOIC Package)
*
Maximum Ratings are those values beyond witch damage to the device may occur.
Functional operation should be restricted to the Recommended Operating Conditions.
+Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C
SOIC Package: : - 7 mW/°C from 65° to 125°C
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
V
CC
DC Supply Voltage (Referenced to GND)
V
IN
, V
OUT
DC Input Voltage, Output Voltage (Referenced to
GND)
T
A
Operating Temperature, All Package Types
t
r
, t
f
Input Rise and Fall Time (Figure 1)
Min
4.5
0
-55
0
Max
5.5
V
CC
+125
500
Unit
V
V
°C
ns
2
IN74HCT109
DC ELECTRICAL CHARACTERISTICS(Voltages
Referenced to GND)
Guaranteed Limit
V
CC
Unit
Symb Parameter
Test Conditions
V
≤85
≤125
25
°C
ol
to
°C
°C
-55°C
V
OUT
=0.1 V or V
CC
-0.1 V
V
IH
Minimum
4.5
2.0
2.0
2.0
V
High-Level
5.5
2.0
2.0
2.0
I
OUT
≤
20
µA
Input Voltage
V
OUT
=0.1 V or V
CC
-0.1 V
V
IL
Maximum
4.5
0.8
0.8
0.8
V
Low -Level
5.5
0.8
0.8
0.8
I
OUT
≤
20
µA
Input Voltage
V
IN
=V
IH
or V
IL
V
OH
Minimum
4.5
4.4
4.4
4.4
V
High-Level
5.5
5.4
5.4
5.4
I
OUT
≤
20
µA
Output
Voltage
V
IN
=V
IH
or V
IL
4.5
3.98
3.84
3.7
I
OUT
≤
4.0 mA
V
IN
= V
IL
or V
IH
V
OL
Maximum
4.5
0.1
0.1
0.1
V
Low-Level
5.5
0.1
0.1
0.1
I
OUT
≤
20
µA
Output
Voltage
V
IN
= V
IL
or V
IH
4.5
0.26
0.33
0.4
I
OUT
≤4.0
mA
V
IN
=V
CC
or GND
I
IN
Maximum
5.5
±0.1
±1.0
±1.0
µA
Input
Leakage
Current
V
IN
=V
CC
or GND
I
CC
Maximum
5.5
4.0
40
80
µA
Quiescent
I
OUT
=0µA
Supply
Current (per
Package)
Additional
V
IN
= 2.4 V, Any One Input
≥-55°C
25°C to 125°C
µA
∆I
CC
Quiescent
V
IN
=V
CC
or GND, Other
Inputs
5.5
2.9
2.4
Supply
I
OUT
=0µA
Current
This device contains protection circuitry to guard against damage due to high static
voltages or electric fields. However, precautions must be taken to avoid applications of any voltage
higher than maximum rated voltages to this high-impedance circuit. For proper operation, V
IN
and
V
OUT
should be constrained to the range GND≤(V
IN
or V
OUT
)≤V
CC
.
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or
V
CC
). Unused outputs must be left open.
3
IN74HCT109
AC ELECTRICAL CHARACTERISTICS(V
CC
=5.5 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Unit
Symbol
Parameter
≤85
≤125
25
°C
to
°C
°C
-55°C
f
max
Maximum Clock Frequency (50% Duty
30
24
20
MHz
Cycle) (Figures 1 and 4)
35
44
53
ns
t
PLH
,
Maximum Propagation Delay, Clock to Q
t
PHL
or
Q
(Figures 1 and 4)
46
58
69
ns
t
PHL
Maximum Propagation Delay , Set or
Reset to Q or
Q
(Figures 2 and 4)
t
TLH
, t
THL
Maximum Output Transition Time, Any
15
19
22
ns
Output (Figures 1 and 4)
C
IN
Maximum Input Capacitance
10
10
10
pF
Power Dissipation Capacitance (Per Flip-
Flop)
Used to determine the no-load dynamic
power
consumption:
2
P
D
=C
PD
V
CC
f+I
CC
V
CC
+∆I
CC
V
CC
Typical @25°C,V
CC
=5.0
V
60
C
PD
pF
TIMING REQUIREMENTS
(V
CC
=5.5 V
±
10%, C
L
=50pF,Input t
r
=t
f
=6.0 ns)
Guaranteed Limit
Symbol
Parameter
25
°C
to
≤85°C
≤125°C
-55°C
t
SU
Minimum Setup Time, J
20
25
30
or K to Clock (Figure 3)
t
h
Minimum Hold Time,
5
5
5
Clock to J or K (Figure 3)
5
5
5
t
rec
Minimum
Recovery
Time, Set or Reset
Inactive to Clock (Figure
2)
t
w
Minimum Pulse Width,
16
20
24
Set or Reset (Figure 2)
t
w
Minimum
Pulse
16
20
24
Width,Clock (Figure 1)
t
r,
t
f
Maximum Input Rise and
500
500
500
Fall Times (Figure 1)
Unit
ns
ns
ns
ns
ns
ns
4
IN74HCT109
Figure 1. Switching Waveforms
Figure 2. Switching Waveforms
Figure 3. Switching Waveforms
Figure 4. Switching Waveforms
EXPANDED LOGIC DIAGRAM
5
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