IZ74LV164 datasheet, PDF - EEWORLD Datasheet

TECHNICAL DATA

IN74LV164

8-BIT SERIAL-IN/PARALLEL-OUT SHIFT REGISTER

The IN74LV164 is a low-voltage Si-gate CMOS device and is pin

and function compatible with the IN74HC/HCT164.

The IN74LV164 is an 8-bit edge-triggered shift register with serial

data entry and an output from each of the eight stages. Data is entered

serially through one of two inputs (DSA or DSB); either input can be

used as an active HIGH enable for data entry through the other input.

Both inputs must be connected together or an unused input must be tied

HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition

of the clock (CP) input and enters into Q

0

, which is the logical AND of

the two data inputs (DSA, DSB ) that existed one set-up time prior to the

rising clock edge.

A LOW on the master reset (MR) input overrides all other inputs

and clears the register asynchronously, forcing all outputs LOW.

•

Outputs Directly Interface to CMOS, NMOS, and TTL

Operating Voltage Range: 1.2 to 5.5 V

Low Input Current: 1.0

µA,

0.1

µÀ

at Ò = 25

°Ñ

Output Current: 6 mA at V

CC

= 3.0 V; 12 mA at V

CC

= 4.5 V

High Noise Immunity Characteristic of CMOS Devices

N SUFFIX

PLASTIC DIP

14

1

14

1

ORDERING INFORMATION

D SUFFIX

SO

IN74LV164N

IN74LV164D

IZ74LV164

Plastic DIP

SOIC

chip

T

A

= -40° to 125° C for all packages

PIN ASSIGNMENT

DSA 1

DSB

2

3

4

5

6

7

14

13

12

11

10

9

8

V

CC

Q7

Q6

Q5

Q4

MR

CP

LOGIC DIAGRAM

Q0

Q1

1

SERIAL DSA

DATA

2

INPUTS DSB

Q2

2 Q0

DATA

4

Q1

Q3

GND

PARALLEL

DATA

OUTPUTS

5 Q2

6 Q3

10 Q 4

11 Q 5

12 Q 6

CP

8

13 Q 7

FUNCTION TABLE

Inputs

Outputs

DSB

X

L

H

L

H

Q0

L

H

Q1 ... Q7

L … L

Q0 ... Q6

MR

L

H

CP

X

DSA

X

L

H

MR

9

PIN 14=V

CC

PIN 7 = GND

H

H = high voltage level

L = low voltage level

X = don’t care

INTEGRAL

1

IN74LV164

MAXIMUM RATINGS

*

Symbol

V

CC

I

IK

*

1

I

OK

*

2

I

O

*

3

I

CC

I

GND

P

D

DC supply voltage

DC Input diode current

DC Output diode current

DC Output source or sink current

V

CC

current

GND current

Power dissipation per package: *

4

Plastic DIP

SO

Storage Temperature

Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO

Package) from Case for 4 Seconds

Parameter

Value

-0.5 to + 7.0

±20

±50

±25

±50

750

500

-65 to +150

260

°C

Unit

V

mA

mW

Tstg

T

L

*

Maximum Ratings are those values beyond which damage to the device may occur.

Functional operation should be restricted to the Recommended Operating Conditions.

*

1

V

I

< -0.5 V or V

I

> V

CC

+ 0.5 V.

*

2

V

O

< -0.5 V or V

O

> V

CC

+ 0.5 V.

*

3

-0.5 V < V

O

< V

CC

+ 0.5 V.

*

4

Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C

SO Package: : - 8 mW/°C from 70° to 125°C

RECOMMENDED OPERATING CONDITIONS

Symbol

V

CC

V

I

V

O

T

A

t

r

, t

f

DC Supply Voltage

Input Voltage

Output Voltage

Operating Temperature, All Package Types

Input Rise and Fall Time (Figure 1)

1.0 V

≤

V

CC

< 2.0 V

2.0 V

≤

V

CC

< 2.7 V

2.7 V

≤

V

CC

< 3.6 V

3.6 V

≤

V

CC

≤

5.5 V

Parameter

Min

1.2

0

-40

0

Max

5.5

V

CC

V

CC

+125

500

200

100

50

Unit

V

°C

ns

This device contains protection circuitry to guard against damage due to high static voltages or electric

fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages

to this high-impedance circuit. For proper operation, V

IN

and V

OUT

should be constrained to the range GND≤(V

IN

or

V

OUT

)≤V

CC

.

Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or V

CC

). Unused

outputs must be left open.

INTEGRAL

2

IN74LV164

DC ELECTRICAL CHARACTERISTICS

(Voltages Referenced to GND)

Test

Symbol

Parameter

conditions

V

CC

V

Guaranteed Limit

25°C to -40°C

min

V

IH

HIGH level input

voltage

1.2

2.0

2.7

3.0

3.6

4.5

5.5

1.2

2.0

2.7

3.0

3.6

4.5

5.5

V

I

= V

IH

or V

IL

I

O

= -100

µÀ

1.2

2.0

2.7

3.0

3.6

4.5

5.5

3.0

4.5

1.2

2.0

2.7

3.0

3.6

4.5

5.5

3.0

4.5

5.5

2.7

3.6

0.9

1.4

2.0

3.15

3.85

-

1.05

1.85

2.55

2.85

3.45

4.35

5.35

2.48

3.70

-

max

-

0.3

0.6

0.8

1.35

1.65

-

0.15

0.33

0.40

±0.1

8.0

0.2

85°C

min

0.9

1.4

2.0

3.15

3.85

-

1.0

1.8

2.5

2.8

3.4

4.3

5.3

2.40

3.60

-

max

-

0.3

0.6

0.8

1.35

1.65

-

0.2

0.4

0.55

±1.0

80

0.5

125°C

min

0.9

1.4

2.0

3.15

3.85

-

1.0

1.8

2.5

2.8

3.4

4.3

5.3

2.20

3.50

-

max

-

0.3

0.6

0.8

1.35

1.65

-

0.2

0.5

0.65

±1.0

160

0.85

V

Unit

V

IL

LOW level input

voltage

V

OH

HIGH level output

voltage

V

I

= V

IH

or V

IL

I

O

= -6.0 mÀ

V

I

= V

IH

or V

IL

I

O

= -12.0 mÀ

V

OL

LOW level output

voltage

V

I

= V

IH

or V

IL

I

O

= 100

µÀ

V

I

= V

IH

or V

IL

I

O

= 6.0 mÀ

V

I

= V

IH

or V

IL

I

O

= 12.0 mÀ

I

CC

I

CC1

Input current

Supply current

V

I

= V

CC

or 0 V

V

I

=V

CC

or 0 V

I

O

= 0

µÀ

V

I

=V

CC

– 0.6 V

V

µÀ

mÀ

INTEGRAL

3

IN74LV164

AC ELECTRICAL CHARACTERISTICS

(C

L

=50 pF, t

r

=t

f

= 2.5 ns, R

L

= 1 kΩ)

Test

Symbol

Parameter

conditions

V

CC

V

Guaranteed Limit

25°C to -40°C

min

t

PHL,

t

PLH

Propagation delay , CP to

Qn

V

I

= 0 V or V

1

Figure 1 and 4

1.2

2.0

2.7

3.0

4.5

1.2

2.0

2.7

3.0

4.5

1.2

2.0

2.7

3.0

4.5

1.2

2.0

2.7

3.0

4.5

1.2

2.0

2.7

3.0

4.5

1.2

2.0

2.7

3.0

4.5

1.2

2.0

2.7

3.0

4.5

5.0

V

I

= 0 V or V

CC

5.5

-

100

28

21

17

14

60

19

13

11

9

50

5

70

15

11

9

8

-

max

150

30

23

18

15

150

30

23

18

15

-

2

16

22

27

32

7.0

80

85°C

min

-

130

34

25

20

17

80

22

16

13

11

50

5

100

19

14

11

10

-

max

180

39

29

23

19

180

39

29

23

19

-

1

14

19

24

27

-

125°C

min

-

160

41

30

24

20

100

26

19

15

13

50

5

130

24

18

14

12

-

max

210

49

36

29

24

210

49

36

29

24

-

1

12

16

20

24

-

ns

Unit

t

PHL

Propagation delay , MR to V

I

= 0 V or V

1

Qn

Figure 1 and 4

ns

t

w

Pulse Width, CP or MR

V

I

= 0 V or V

1

Figure 1

ns

t

su

Setup Time, DSA or DSB

to CP

V

I

= 0 V or V

1

Figure 3

ns

t

h

Hold Time, DSA or DSB to V

I

= 0 V or V

1

CP

Figure 3

ns

t

rec

Recovery Time, MR to CP

V

I

= 0 V or V

1

Figure 2

ns

f

max

Clock Frequency

V

I

= 0 V or V

1

Figure 1 and 4

MHz

C

I

C

PD

Input capacitance

Power dissipation

capacitance

pF

INTEGRAL

4

IN74LV164

t

w

tr

CP

10%

V

M

(1 )

tf

90%

V

1

(2)

MR

t

PHL

Q

V

M

(1)

V

1

(2)

GND

V

OH

V

OL

GND

t

w

1/fmax

t

PLH

t

PHL

V

OH

V

OL

V

M

( 1)

Q

V

M

(1 )

t

rec

CP

V

M

(1)

V

1

(2)

GND

Figure 1. Switching Waveforms

Figure 2. Switching Waveforms

TEST POINT

VALID

DSA or DSB

V

M

(1 )

V

1

(2 )

GND

t

su

t

h

V

1

V

M

( 1)

DEVICE

UNDER

TEST

OUTPUT

R

L

*

(2 )

C

L

CP

GND

* Includes all probe and jig capacitance

Figure 3. Switching Waveforms

Note:

(1)

Figure 4. Test Circuit

V

M

= 1.5 V at V

CC

= 2.7 V

V

M

= 0.5

⋅V

CC

at V

CC

=1.2 V, 2.0 V, 3.0 V, 4.5 V

V

1

= V

CC

at V

CC

=1.2 V, 2.0 V, 2.7 V, 4.5 V

V

1

= 2.7 V at V

CC

= 3.0 V

(2)

TIMING DIAGRAM

CP

DSA

DSB

MR

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

INTEGRAL

5

IZ74LV164

IZ74LV164 Overview

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