RM7000B
Preliminary
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
FEATURES
• Dual-Issue symmetric superscalar
microprocessor
•
500MHz max CPU frequency
•
Capable of issuing two instructions
per clock cycle
• Integrated primary and secondary
caches
•
16KB Instruction, 16KB Data, and
256KB on-chip secondary
•
All are 4-way set associative with
32-byte line size
•
Per-line locking in primary and
secondary caches
•
Fast Packet Cache™ increases
system efficiency in networking
applications
• Integrated external cache controller
•
Allows up to 8Mbyte of external
cache for applications with large
data sets
• High-performance system interface
•
1000 Mbyte per-second peak
throughput
125 MHz max. freq., multiplexed
address/data bus (SysAD)
•
Supports two outstanding reads with
out-of-order return
High-performance floating-point unit
•
1000 MFLOPS maximum
•
IEEE754 compliant single and
double precision floating-point
operations
64-bit MIPS instruction set architecture
•
Data PREFETCH instruction allows
the processor to overlap cache miss
latency and instruction execution
•
Single-cycle floating-point multiply-
add
Integrated memory management unit
•
Fully associative TLB
•
64/48 dual entries map 128/96
pages
•
Variable page size
Embedded application enhancements
•
Fourteen fully prioritized vectored
interrupts-10 external, 2 internal, 2
software
•
•
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Specialized DSP integer Multiply-
Accumulate instructions
(MAD/MADU), and three-operand
Multiply instruction (MUL)
I and D Test/Break-point (Watch)
registers for emulation and debug
Performance counter for system
and software tuning and debug
•
PACKAGING
•
•
Fully Static 0.13µ CMOS design
with dynamic power down logic
304 pin TBGA package, 31x31 mm
•
DEVELOPMENT TOOLS
• Operating Systems:
•
Linux by MontaVista and Red Hat
•
VxWorks by Wind River Systems
•
Nucleus by Accelerated Technology
•
Neutrino by QNX Software Systems
• Compiler Suites
•
Algorithmics
•
Green Hills Software
•
BLOCK DIAGRAM
64-bit Integer Unit
Dual-Issue Superscalar
Integer Multiplier
System Control
PC Unit
64-bit FP Unit
Double/Single IEEE754
Instr. Dispatch
I-Cache
16KB, 4-way, lockable
MMU
Fully Assoc., 48 or 64 Entry
D-Cache
16KB, 4-way, lockable
Bus Interface Unit
L3 Cache Control
System Cache (L2)
Int Ctlr
256KB, 4-way, lockable
64-bit
SysA /D Bus & L3 Ctr
NMI, INT9 – INT0
PMC- 2011603(P1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2000
Preliminary
RM7000B
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
Red Hat
• Evaluation Boards and Companion
Chips
•
Galileo Technology
•
EV-64120A-7000: 32/64-bit,
33/66MHz PCI
•
EV-64240-7000: 32/64-bit,
33/66MHz PCI
•
Momentum Computer
•
Ocelot: 6U RM7000 Compact PCI
Single Board Computer
•
•
Logic Analyzers and Emulation
•
HP
•
Tektronix
•
Corelis
•
Crescent Heart Software
APPLICATIONS
•
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Voice Gateways
Multi-Service Access Platforms
DSLAMs/Access Concentrators
Remote Access Switches
Web Switches
Layer 3 Switches
Backbone Switches/Routers
RAIDs
Set Top Boxes
Networked Printers
Cellular Base Stations
TYPICAL APPLICATION
RM7000B
64-Bit
100MHz
64-Bit
100MHz
L3 Cache
Galileo
GT-64120A
SDRAM
PCI Bus
32/64-bit @ 33MHz
64-
bit
PCI-to-PCI
Bridge
32-
bit
Ethernet
MAC
32-
bit
64-
bit
Data
Buffer
8-bit
Boot-Flash
Flash
Disk
Watchdog,
I
2
C & Control
Registers
Ethernet
MAC
Dual UART
Head Office:
PMC-Sierra, Inc.
#105 - 8555 Baxter Place
Burnaby, B.C. V5A 4V7
Canada
Tel: 604.415.6000
Fax: 604.415.6200
To order documentation,
send email to:
document@pmc-sierra.com
or contact the head office,
Attn: Document Coordinator
All product documentation is available
on our web site at:
http://www.pmc-sierra.com
For corporate information,
send email to:
info@pmc-sierra.com
PMC- 2011603(P1)
© Copyright PMC-Sierra, Inc. 2001. All
rights reserved. RM7000B is a trademark of
PMC-Sierra Inc.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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