GENLINX
™
GS9005A
Serial Digital Receiver
DATA SHEET
FEATURES
•
•
•
automatic cable equalization (typically 300m of high
quality cable at 270Mb/s)
fully compatible with SMPTE 259M and operational
to 400 Mb/s
adjustment free receiver when used with the
GS9000B or GS9000S decoder and GS9010A
Automatic Tuning Sub-system
signal strength indicator
selectable cable or direct digital inputs
28 pin PLCC packaging
DEVICE DESCRIPTION
The GS9005A is a monolithic IC designed to receive SMPTE
259M serial digital video signals. This device performs the
functions of automatic cable equalization and data and clock
recovery. It interfaces directly with the
GENLINX™
GS9000B
or GS9000S decoder, and GS9010A Automatic Tuning
Subsystem.
The VCO centre frequencies are controlled by external resistors
which can be selected by applying a two bit binary code to the
Standards Select input pins.
An additional feature is the Signal Strength Indicator output
which provides a 0.5V to 0V analog output relative to V
CC
indicating the amount of equalization being applied to the
signal.
The GS9005A is packaged in a 28 pin PLCC operating from a
single +5 or -5 volt supply.
SPECIAL NOTE:
R
VCO1
and R
VCO2
are functional over a
reduced temperature range of T
A
=0° C to 50° C. R
VCO0
and R
VCO3
are functional over the full temperature range
of T
A
=0° C to 70° C. This limitation does not affect
operation with the GS9010A ATS.
GS9005A
SIGNAL
STRENGTH
INDICATOR
28
FILTER
CONTROL
PEAK
DETECTOR
VOLTAGE
VARIABLE
FILTER
CABLE 8,9
IN
EQUALIZER
DIGITAL 5,6
IN
24
DATA
LATCH
25
22
23
Σ
DC
RESTORER
ANALOG
DIGITAL
SELECT
LOGIC
COMPARATOR
AGC
2 CAPACITOR
•
•
•
APPLICATIONS
• 4ƒ
SC
, 4:2:2 and 360 Mb/s serial digital interfaces
ORDERING INFORMATION
PART NUMBER
GS9005ACPJ
GS9005ACTJ
PACKAGE
28 Pin PLCC
28 Pin PLCC Tape
TEMPERATURE
0
O
C to 70
O
C
0
O
C to 70
O
C
16
OUTPUT 'EYE'
MONITOR
1
A/D
SERIAL DATA
SERIAL DATA
SERIAL CLOCK
SERIAL CLOCK
PHASE
COMPARATOR
CARRIER
DETECT
19
CARRIER
DETECT
CHARGE
PUMP
10
÷2
ƒ/2 ENABLE
20
LOOP
FILTER 12
PLL
13 14 15 17
VCO
STANDARD
SELECT
21
SS0
SS1
Revision Date: August 1997
FUNCTIONAL BLOCK DIAGRAM
Document No. 520 - 28 - 11
GENNUM CORPORATION P.O. Box 489, Stn A, Burlington, Ontario, Canada L7R 3Y3 tel. (905) 632-2996 fax: (905) 632-5946
Gennum Japan Corporation: A-302 Miyamae Village, 2-10-42 Miyamae, Suginami-ku, Tokyo 168, Japan
tel. (03) 3334-7700
fax (03) 3247-8839
ABSOLUTE MAXIMUM RATINGS
PARAMETER
Supply Voltage
Input Voltage Range (any input)
DC Input Current (any one input)
Power Dissipation
Operating Temperature Range
Storage Temperature Range
Lead Temperature (soldering, 10 seconds)
VALUE / UNITS
5.5 V
V
CC
+0.5 to V
EE
-0.5 V
5 mA
750 mW
0°C
≤
T
≤70°C
A
CAUTION
ELECTROSTATIC
SENSITIVE DEVICES
DO NOT OPEN PACKAGES OR HANDLE
EXCEPT AT A STATIC-FREE WORKSTATION
-65°C
≤
T
S
≤150°C
260°C
GS9005A RECEIVER DC ELECTRICAL CHARACTERISTICS
V
S
= 5V, T
A
= 0°C to 70°C, R
L
= 100Ω to (V
CC
- 2V) unless otherwise shown.
PARAMETER
Supply Voltage
Power Consumption
Supply Current (Total)
Serial Data &
Clock Output
Logic Inputs
(1, 10, 20, 21)
Carrier Detect
Output Voltage
Signal Strength
Indicator Output
Direct Digital Input
Levels (5, 6)
- High
- Low
- High
- Low
SYMBOL
V
S
P
D
I
S
V
OH
V
OL
V
IH MIN
V
IL MAX
V
CDL
V
CDH
V
SS
V
DDI
CONDITIONS
Operating Range
MIN
4.75
-
-
TYP
5.0
500
122
-
-
-
-
0.2
5.0
-
-
MAX
5.25
700
160
-0.88
-1.6
-
+0.8
0.4
-
0
2000
UNITS
V
mW
mA
V
V
V
V
V
V
V
mVp-p
NOTES
see Figure13
with respect to V
CC
with respect to V
CC
with respect to V
EE
with respect to V
EE
with respect to V
EE
Open
Collector - Active High
T
A
= 25°C
T
A
= 25°C
-1.025
-1.9
+2.0
-
R
L
= 10 kΩ to V
CC
-
4.0
See Note 2
-0.6
200
with respect to V
CC
Differential Drive
GS9005A RECEIVER AC ELECTRICAL CHARACTERISTICS
V
S
= 5V, T
A
= 0°C to 70°C, R
L
= 100Ω to (V
CC
- 2V) unless otherwise shown.
PARAMETER
Serial Data Bit Rate
Serial Clock Frequency
Output Signal Swing
Serial Data to Serial Clock
Synchronization
Lock Times
Equalizer Gain
Jitter
SYMBOL
BR
SDO
ƒ
SLK
V
O
t
d
CONDITION
T
A
= 25°C
T
A
= 25°C
T
A
= 25°C
See Waveforms
MIN
100
100
700
-
TYP
-
-
800
-500
MAX
400
400
900
-
UNITS
Mb/s
MHz
mV p-p
ps
NOTES
see Figure11
see Figure12
Data lags Clock
t
LOCK
AV
EQ
t
J
R
IN
C
IN
V
OEM
See Note 1
T
A
= 25°C
T
A
= 25°C
0 metres, 270 Mb/s
T
A
= 25˚C
T
A
= 25˚C
R
L
= 50Ω to V
CC
-
30
-
-
36
±
100
10
-
-
µs
dB
ps p-p
Ω
pF
mVp-p
at 135 MHz
see Figure15
Input Resistance (SDI/SDI)
Input Capacitance (SDI/SDI)
Output Eye Monitor
3k
-
-
5k
1.8
40
-
-
-
see Figure14
see Figure14
NOTES: 1.
Switching between two sources of the same data rate.
2.
With weaker signals V
SS
approaches V
CC
.
520 - 28 - 11
2
GS9005A Re - clocking Receiver - Detailed Device Description
The GS9005A Reclocking Receiver is a bipolar integrated
circuit containing a built-in cable equalizer and circuitry
necessary to re-clock and regenerate the NRZI serial data
stream.
Packaged in a 28 pin PLCC, the receiver operates from a
single five volt supply at data rates in excess of 400 Mb/s.
Typical power consumption is 500 mW. Typical output jitter is
±
100 ps at 270 Mb/s.
Serial Digital signals are applied to either a built-in analog
cable equalizer via the SDI and SDI inputs (pins 8,9) or via the
direct digital inputs DDI and DDI (pins 5,6).
Cable Equalizer
The Serial Digital signal is connected to the input either
differentially or single ended with the unused input being
decoupled. The equalized signal is generated by passing the
cable signal through a voltage variable filter having a
characteristic which closely matches the inverse cable loss
characteristic. Additionally, the variation of the filter
characteristic with control voltage is designed to imitate the
variation of the inverse cable loss characteristic as the cable
length is varied.
The amplitude of the equalized signal is monitored by a peak
detector circuit which produces an output current with a
polarity corresponding to the difference between the desired
peak signal level and the actual peak signal level. This output
is integrated by an external AGC filter capacitor (AGC
CAP pin 2), providing a steady control voltage for the voltage
variable filter.
A separate signal strength indicator output, (SSI pin 28),
proportional to the amount of AGC is also provided. As the
filter characteristic is varied automatically by the application of
negative feedback, the amplitude of the equalized signal is
kept at a constant level which is representative of the original
amplitude at the transmitter.
The equalized signal is then DC restored, effectively restoring
the logic threshold of the equalized signal to its correct level
irrespective of shifts due to AC coupling.
As the final stage of signal conditioning, a comparator converts
the analog output of the DC restorer to a regenerated digital
output signal.
An OUTPUT 'EYE' MONITOR (pin 16), allows verification of
signal integrity after equalization but before reslicing.
Analog/Digital Select
A 2:1 multiplexer selects either the equalized (analog) signal
or a differential ECL data (digital) signal as input to the
reclocker PLL.
3
A logical HIGH applied to the Analog/Digital Select input (1)
routes the equalized signal while a logic LOW routes the
direct digital signal to the reclocker.
Phase Locked Loop
The phase comparator itself compares the position of
transitions in the incoming signal with the phase of the local
oscillator (VCO). The error-correcting output signals are fed
to the charge pump in the form of short pulses. The charge
pump converts these pulses into a “charge packet” which is
accurately proportional to the system phase error.
The charge packet is then integrated by the second-order
loop filter to produce a control voltage for the VCO.
During periods when there are no transitions in the signal, the
loop filter voltage is required to hold precisely at its last value
so that the VCO does not drift significantly between corrections.
Commutating diodes in the charge pump keep the output
leakage current extremely low, minimizing VCO frequency
drift.
The VCO is implemented using a current-controlled
multivibrator, designed to deliver good stability, low phase
noise and wide operating frequency capability. The frequency
range is design-limited to
±
10% about the oscillator centre
frequency.
VCO Centre Frequency Selection
The centre frequency of theVCO is set by one of four external
current reference resistors (RVCO0-RVCO3) connected to
pins 13,14,15 or 17. These are selected by two logic inputs
SS0 and SS1 (pins 20, 21) through a 2:4 decoder according
to the following truth table.
SS1
0
0
1
1
SS0
0
1
0
1
Resistor Selected
RVCO0 (13)
RVCO1 (14)
RVCO2 (15)
RVCO3 (17)
As an alternative, the GS9010A Automatic Tuning Sub-system
and the GS9000B or GS9000S Decoder may be used in
conjunction with the GS9005A to obtain adjustment free and
automatic standard select operation (see Figure 20).
With the VCO operating at twice the clock frequency, a clock
phase which is centred on the eye of the locked signal is used
to latch the incoming data, thus maximising immunity to
jitter-induced errors. The alternate phase is used to latch the
output re-clocked data SDO and SDO (pins 25, 24). The true
and inverse clock signals themselves are available from the
SCO and SCO pins 23 and 22.
520 - 28 - 11
AGC
V
CC1
V
EE1
CAP
tD
tD
A/D
SSI
V
EE2
27
V
CC4
26
25
24
23
SD0
SD0
SC0
SC0
SS1
SS0
CD
4
SERIAL
DATA OUT
(SD0)
3
2
28
DDI
DDI
V
CC2
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SERIAL
CLOCK OUT
(SCK)
50%
50%
SDI
SDI
GS9005A
TOP VIEW
22
21
20
19
ƒ/2 EN
Fig.1 Waveforms
V
EE3
LOOP R
VCO0
R
VCO1
R
VCO2
OEM R
VCO3
V
CC3
FILT
Fig. 2 GS9005A Pin Connections
GS9005 & GS9005A PIN DESCRIPTIONS
PIN NO.
1
SYMBOL
A/D
TYPE
Input
DESCRIPTION
Analog/Digital Select.
TTL compatible input used to select the input signal source. A logic HIGH routes the
Equalizer inputs (pins 8 and 9) to the PLL and a logic LOW routes the Direct Digital inputs (pins 5 and 6)
to the PLL.
2
3
4
5,6
AGC CAP
V
EE1
V
CC1
DDI/DDI
Input
Input
AGC Capacitor.
Connection for the AGC capacitor.
Power Supply.
Most negative power supply connection. (Equalizer)
Power Supply.
Most positive power supply connection. (Equalizer)
Direct Data Inputs (true and inverse).
Pseudo-ECL, differential serial data inputs. These are selected
when the A/D input (pin 1) is at logic LOW and are self biased to 1.2 volts below V
CC
. They may be
directly driven from true ECL drivers when V
EE
= -5V and V
CC
= 0 V.
7
8,9
V
CC2
SDI/SDI
Input
Power Supply.
Most positive power supply connection. ( Phase detector, A/D select, carrier detect).
Serial Data Inputs (true and inverse).
Differential analog serial data inputs. Inputs must be AC
coupled and may be driven single ended. These inputs are selected when the A/D input (pin 1) is
logic HIGH.
10
11
12
13
ƒ/2 EN
V
EE3
LOOP FILT
R
VCO0
Input
Input
ƒ/2 Enable-TTL
compatible input used to enable the divide by 2 function.
Power Supply.
Most negative power supply connection. (VCO, Mux, Standard Select)
Loop Filter.
Node for connecting the loop filter components.
VCO Resistor 0.
Analog current input used to set the centre frequency of the VCO when the two
Standard Select bits (pins 20 and 21) are set to logic 0,0. A resistor is connected from this pin to V
EE
.
14
R
VCO1
Input
VCO Resistor 1.
Analog current input used to set the centre frequency of the VCO when Standard
Select bit 0 (pin 20) is set HIGH and bit 1 (pin 21) is set LOW. A resistor is connected from this pin to V
EE
.
15
R
VCO2
Input
VCO Resistor 2.
Analog current input used to set the centre frequency of the VCO when Standard
Select bit 0 (pin 20) is set LOW and bit 1 (pin 21) is set HIGH. A resistor is connected from this pin to V
EE
.
16
17
OEM
R
VCO3
Output
Input
Output Eye Monitor
Analog voltage representing the serial bit stream after equalization but before reslicing.
VCO Resistor 3.
Analog current input used to set the centre frequency of the VCO when the two
Standard Select bits (pins 20 and 21) are set HIGH. A resistor is connected from this pin to V
EE
.
520 - 28 - 11
4
GS9005 & GS9005A PIN DESCRIPTIONS cont.
PIN NO
18
19
SYMBOL
V
CC3
CD
TYPE
DESCRIPTION
Power Supply.
Most positive power supply connection. (VCO, MUX, standards select).
Output
Carrier Detect.
Open collector output which goes HIGH when a signal is present at either the Serial
Data inputs or the Direct Digital inputs. This output is used in conjunction with the GS9000B or GS9000S
in the Automatic Standards Select Mode to disable the 2 bit standard select counter. This pin should
see a low impedance (e.g. 1nF to AC Gnd)
20,21
SS0, SS1 Inputs
Standard Select Inputs.
TTL inputs to the 2:4 multiplexer used to select one of four VCO centre
frequency setting resistors (R
VCO0
- R
VCO3
). When both SS0 and SS1 are LOW, R
VCO0
is selected.
When SS0 is HIGH and SS1 is LOW, R
VCO1
is selected. When SS0 is LOW and SS1 is HIGH, R
VCO2
is selected and when both SS0 and SS1 are HIGH, R
VCO3
is selected. These pins should see a
low impedance (e.g. 1nF to AC Gnd)
22,23
SCO/SCO Outputs
Serial Clock Outputs (inverse and true).
Pseudo-ECL differential outputs of the extracted serial clock.
These outputs require 390
Ω
pull-down resistors to V
EE
.
24,25
SDO/SDO Outputs
Serial Data Outputs (inverse and true).
Pseudo-ECL differential outputs of the regenerated serial data.
These outputs require 390
Ω
pull-down resistors to V
EE
.
26
27
28
V
CC4
V
EE2
SSI
Power Supply.
Most positive power supply connection. (ECL outputs)
Power Supply.
Most negative power supply connection. (Phase detector, A/D select, Carrier detect)
Signal Strength Indicator.
Analog output which indicates the amount of AGC action. This output
indirectly indicates the amount of equalization and thus cable length.
INPUT / OUTPUT CIRCUITS
V
CC
+
-
V
CC
V
CC
16µA
2k
2k
1.2V
VCC
1k
1k
A/D
Pin 1
DDI
Pin 5
DDI
Pin 6
+
1.6V
-
50µA
380µA
Fig. 3 Pins 1, 5 and 6
5
520 - 28 - 11
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