February 2007
rev 1.4
Low Frequency EMI Reduction
Features
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ASM3P2531A
dependent signals. It allows significant system cost
savings by reducing the number of circuit board layers
and
shielding
traditionally
required
to
pass
EMI
regulations.
The ASM3P2531A modulates the output of a single PLL
in order to spread the bandwidth of a synthesized clock,
thereby decreasing the peak amplitudes of its harmonics.
This result in significantly lower system EMI compared to
the typical narrow band signal produced by oscillators
and most clock generators. Lowering EMI by increasing
a signal’s bandwidth is called spread spectrum clock
generation.
The ASM3P2531A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all-digital method.
FCC approved method of EMI attenuation.
Generates a low EMI spread spectrum of the
input clock frequency.
Optimized for input frequency range between
27MHz – 55MHz.
Internal loop filter minimizes external
components and board space.
Frequency Deviation: ±1.7%.
Low inherent Cycle-to-cycle jitter.
3.3 V ± 0.3V Operating Voltage.
Ultra low power CMOS design:3.0 mA @ 3.3 V.
Supports notebook VGA and other LCD timing
controller applications.
Available in 8-pin SOIC and TSSOP Packages.
Product Description
The ASM3P2531A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. It reduces electromagnetic
interference (EMI) at the clock source allowing system-
wide reduction of EMI of downstream clock and data
Applications
The ASM3P2531A is targeted toward the notebook VGA
chip and other displays using an LVDS interface, PC
peripheral devices, and embedded systems.
Block Diagram
V
DD
STOP
Modulation
CLKIN
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
V
SS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
•
Tel: 408-879-9077
•
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
February 2007
rev 1.4
Pin Configuration (8-pin SOIC and TSSOP Packages)
ASM3P2531A
CLKIN
V
DD
V
SS
ModOUT
1
2
3
4
ASM3P2531A
8
7
6
5
NC
NC
NC
STOP
Spread Range Selection, V
DD
= 3.3 V
CLKIN frequency
27MHz – 55MHz
Spreading range
± 1.7%
Modulation rate
(CLKIN/1280) KHz
Pin Description
Pin#
1
2
3
4
Pin Name
CLKIN
V
DD
V
SS
ModOUT
Type
I
P
P
O
External reference frequency input.
Power supply for the entire chip.
Ground to entire chip.
Description
Spread spectrum clock output or reference output.( Refer Standby Mode Selection.)
5
6
7
8
STOP
NC
NC
NC
I
-
-
-
Active LOW signal. When HIGH, enables ModOUT and when LOW, ModOUT would be
LOW.
No connect.
No connect.
No connect.
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
2 of 8
February 2007
rev 1.4
Schematic for a Typical Application
Input clock 27MHz – 55MHz
VDD
FB : Optional ferrite bead
FB
0.1uF
GND
4
EMI reduced clock output
27MHz – 55MHz
ModOUT
STOP
5
ASM3P2531A
1
2
3
CLKIN
NC
8
7
6
V
DD
NC
ASM3P2531A
V
SS
NC
VDD
0
Ω
0
Ω
Use either pull-up or pull-down
resistors with 0Ω
Absolute Maximum Ratings
Symbol
V
DD
, V
IN
T
STG
T
A
T
s
T
J
T
DV
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Parameter
Voltage on any pin with respect to Ground
Rating
-0.5 to +4.6
-65 to +125
-40 to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
3 of 8
February 2007
rev 1.4
DC Electrical Characteristics
Symbol
V
IL
V
IH
I
IL
I
IH
V
OL
V
OH
I
DD
I
CC
V
DD
t
ON
Z
OUT
Input low voltage
Input high voltage
Input low current
Input high current
Output low voltage
Output high voltage
Dynamic supply current
Operating voltage
Power-up time (first locked cycle after power up)
Clock output impedance
V
DD
= 3.3V, I
OL
= 6 mA
V
DD
= 3.3V, I
OH
= 15 mA
3.3V and 15pF loading
2.5
3.0
10
3.0
3.3
0.18
50
ASM3P2531A
Parameter
Min
V
SS
- 0.3
2.0
Typ
Max
0.8
V
DD
+ 0.3
-35
35
0.4
Unit
V
V
µA
µA
V
V
mA
Static supply current standby mode
14
3.6
mA
V
mS
Ω
AC Electrical Characteristics
Symbol
f
IN
f
OUT
t
LH
1
Parameter
Input frequency
Output frequency
Output rise time
Output fall time
Jitter (Cycle to cycle)
Output duty cycle
Measured from 0.8 V to 2.0 V
Measured from 2.0 V to 0.8 V
Min
27
27
0.4
0.4
45
Typ
Max
55
55
Unit
MHz
MHz
nS
nS
pS
%
0.6
0.6
50
1.2
1.2
360
55
t
HL 1
t
JC
T
D
Note 1: t
LH
and t
HL
are measured into a capacitive load of 15pF
Low Frequency EMI Reduction
Notice: The information in this document is subject to change without notice.
4 of 8
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