tm
•
•
•
•
•
TE
CH
T431616A
SDRAM
FEATURES
3.3V power supply
Clock cycle time : 6 / 7 / 8 / 10 ns
Dual banks operation
LVTTL compatible with multiplexed address
All inputs are sampled at the positive going
edge of system clock
•
Burst Read Single-bit Write operation
•
DQM for masking
•
Auto refresh and self refresh
•
32ms refresh period (2K cycle)
•
MRS cycle with address key programs
- CAS Latency ( 2 & 3 )
- Burst Length ( 1 , 2 , 4 , 8 & full page)
- Burst Type (Sequential & Interleave)
•
Available package type in 50 pin TSOP(II)
and 60-pin CSP.
•
Operating temperature :
- -5 ~ +70
°C
-
-40 ~ +85
°C
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T431616A is 16,777,216 bits synchronous
high data rate Dynamic RAM organized as
2 x 524,288 words by 16 bits , fabricated with high
performance CMOS technology . Synchronous
design allows precise cycle control with the use of
system clock I/O transactions are possible on every
clock cycle . Range of operating frequencies ,
programmable burst length and programmable
latencies allow the same device to be useful for a
variety of high bandwidth , high performance
memory system applications.
PART NUMBER EXAMPLES
PART NO.
CLOCK
CYCLE TIME
7ns
7ns
7ns
7ns
MAX
FREQUENCY
PACKAGE
TSOP-II
CSP
TSOP-II
CSP
OPERATING
TEMPERATURE
T431616A-7S
T431616A-7C
T431616A-7SI
T431616A-7CI
143 MHz
143 MHz
143 MHz
143 MHz
-5 ~ +70
°C
-5 ~ +70
°C
-40 ~ +85
°C
-40 ~ +85
°C
Taiwan Memory Technology, Inc. reserves the right
P. 1
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
tm
V
DD
DQ0
DQ1
V
SSQ
DQ2
DQ3
V
DDQ
DQ4
DQ5
V
SSQ
DQ6
DQ7
V
DDQ
LDQM
WE
CAS
RAS
CS
BA
A10/AP
A0
A1
A2
A3
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
TE
CH
T431616A
PIN ARRANGEMENT
(TSOP-II
Top View)
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
Vss
DQ15
DQ14
V
SSQ
DQ13
DQ12
V
DDQ
DQ11
DQ10
V
SSQ
DQ9
DQ8
V
DDQ
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4
Vss
50PINTSOP(II)
(400mil x 825mil)
(0.8 mm PIN PITCH)
(CSP Bottom View)
VDD
A1
A10/AP
N.C
CS
CAS
WE
N.C
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
VDD
7
6
A3
A2
A0
N.C
N.C
RAS
LDQM
N.C
N.C
VSSQ
VDDQ
DQ4
VSSQ
VDDQ
DQ0
5
4
3
A4
A5
A7
A9
N.C
CLK
UDQM
N.C
N.C
VDDQ
VSSQ
DQ11
VDDQ
VSSQ
DQ15
2
1
VSS
A6
A8
BA
CKE
N.C
N.C
N.C
DQ8
DQ9
DQ10
DQ12
DQ13
DQ14
VSS
R
P
N M L K
J
H G
F E
D C
B A
Taiwan Memory Technology, Inc. reserves the right
P. 2
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
tm
TE
CH
T431616A
BLOCK DIAGRAM
I/O Control
LW E
Bank Select
Data Input Register
LDQM
Row Decoder
Row Buffeer
Refresh Counter
Sense AMP
512K x 16
Output Buffer
DQ i
Address Register
CLK
512K x 16
AD D
LCBR
LRAS
Colum n Decoder
Col. Buffer
Latency & Burst Length
LCKE
LRAS
LCBR
LW E
LCAS
Tim ing Register
Program m ing Register
LW CBR
LDQM
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
Taiwan Memory Technology, Inc. reserves the right
P. 3
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
tm
PIN
CLK
TE
CH
T431616A
PIN DESCRIPTION
NAME
System Clock
Chip Select
INPUT FUNCTION
Active on the positive going edge to sample all input.
Disables or enables device operation by masking or enabling all input
except CLK,CKE and L(U)DQM
Masks system clock to freeze operation from the next clock cycle.
CS
CKE
Clock Enable
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A0 ~ A10/AP
BA
Address
Bank Select Address
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10,column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
RAS
Row Address Strobe
with
RAS
low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
CAS
Column Address Strobe
with
CAS
low.
Enables column access .
Enables write operation and row precharge.
Latches data in starting from
CAS
,
WE
active.
Makes data output Hi-Z,
t
SHZ
after the clock and masks the output.
Blocks data input when L(U)DQM active.
Data inputs/outputs are multiplexed on the same pins.
WE
L(U)DQM
DQ0 ~ DQ15
V
DD
/V
SS
V
DDQ
/V
SSQ
Write Enable
Data Input/Output
Mask
Data Input/Output
Data Output
Power/Ground
No
Connection/Reserved
for Future Use
Power Supply/Ground
Power and ground for the input buffers and the core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
This pin is recommended to be left No Connection on the device.
N.C/RFU
Taiwan Memory Technology, Inc. reserves the right
P. 4
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
tm
Parameter
TE
CH
T431616A
Symbol
V
IN
,V
OUT
V
DD
,V
DDQ
Iout
P
D
TOPR
Tstg
Value
-1.0 to 4.6
-1.0 to 4.6
50
1
-5 to +70 / -40 to +85
-55 to +125
Unit
V
V
mA
W
°C
°C
ABSOLUTE MAXIMUM RATINGS
Voltage on Any Pin Relative To Vss
Supply Voltage Relative To Vss
Short circuit Output Current
Power Dissipation
Operating Temperature
Storage Temperature
Note :
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(T
A
= -5 to +70
°C
/ -40 to +85
°C
, Voltage referenced to V
SS
=0V)
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output logic high voltage
Output logic low voltage
Input leakage current
Output leakage current
Symbol
V
DD
,V
DDQ
V
IH
V
IL
V
OH
V
OL
I
IL
I
OL
Min.
3.0
2.0
-0.3
2.4
-
-5
-5
Typ
3.3
3.0
0
-
-
-
-
Max.
3.6
V
DD
+0.3V
0.8
-
0.4
5
5
Unit
V
V
V
V
V
uA
uA
1
2
I
OH
=-2mA
I
OL
=2mA
3
4
Notes
Note :
1. V
IH
(max) = 4.6V AC for pulse width
≤
10ns acceptable.
2. V
IL
(min) = -1.0V AC for pulse width
≤
10ns acceptable.
3. Any input 0V
≤
V
IN
≤
V
DD
+ 0.3V , all other pin are not under test = 0V.
4. Dout = disable, 0V
≤
V
OUT
≤
V
DD .
CAPACITANCE
(T
A
=25
°C
,V
DD
=3.3V, f = 1MHz)
Pin
CLOCK
ADDRESS
DQ0 ~ DQ15
RAS,CAS,WE,CS,CKE,LDQM,
UDQM
Symbol
C
CLK
C
ADD
C
OUT
C
IN
Min
2.5
2.5
4.0
2.5
Max
4.0
5.0
6.5
5.0
Unit
pF
pF
pF
pF
Taiwan Memory Technology, Inc. reserves the right
P. 5
to change products or specifications without notice.
Publication Date: DEC. 2000
Revision: C
NXP MCU
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