4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR041 / SST30VR043
SST30VR041/0434 Mb Mask ROM (x8) + 1 Mb / 256 Kbit SRAM (x8) Combo
Preliminary Specifications
FEATURES:
• ROM + SRAM ROM/RAM Combo
– SST30VR041: 512K x8 ROM + 128K x8 SRAM
– SST30VR043: 512K x8 ROM + 32K x8 SRAM
• ROM/RAM combo on a monolithic chip
• Equivalent ComboMemory (Flash + SRAM):
SST31LF041A for code development and
pre-production
• Wide Operating Voltage Range: 2.7-3.3V
• Chip Access Time
– SST30VR041 70 ns and 150 ns
– SST30VR043 150 ns
• Low Power Dissipation:
– Standby: 1.0 µW (Typical)
– Operating: 3.0 mW (Typical)
• Fully Static Operation
– No clock or refresh required
• Three state Outputs
• Packages Available
– 32-pin TSOP (8mm x14mm)
PRODUCT DESCRIPTION
The SST30VR041/043 are ROM/RAM combo chips con-
sisting of 4 Mbit Read Only Memory organized as 512
KBytes and a Static Random Access Memory organized
as either 128 or 32 KBytes. Output Enable Input (OE#) is
pin-shared with RAMCS# (RAM Enable Input) signal in
order to maintain the standard 32-pin TSOP package.
The device is fabricated using SST’s advanced CMOS low
power process technology.
The SST30VR041/043 have an output enable input for pre-
cise control of the data outputs. It also has two (2) separate
chip enable inputs for selection of either RAM or ROM and
for minimizing current drain during power-down mode.
The SST30VR041/043 is particularly well suited for use in
low voltage (2.7-3.3V) supplies such as pagers, organizers
and other handheld applications.
F
UNCTIONAL
B
LOCK
D
IAGRAM
RAMCS#
ROMCS#
OE#/RAMCS#
WE#
Control
Circuit
OE#
WE#
Data Buffer
RAM
Address Buffer
DQ7-DQ0
ROMCS#
OE#
AMS-A0
ROM
Note: AMS = Most Significant Address
381 ILL B1.2
©2001 Silicon Storage Technology, Inc.
S71134-02-000 4/01
381
1
The SST logo and SuperFlash are registered trademarks of Silicon Storage Technology, Inc.
ComboMemory is a trademark of Silicon Storage Technology, Inc.
These specifications are subject to change without notice.
4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR041 / SST30VR043
Preliminary Specifications
A11
A9
A8
A13
A14
A17
WE#
VDD
A18
A16
A15
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Standard Pinout
Top View
Die Up
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
381 ILL F01.0
OE#/RAMCS#
A10
ROMCS#
DQ7
DQ6
DQ5
DQ4
DQ3
VSS
DQ2
DQ1
DQ0
A0
A1
A2
A3
FIGURE 1: P
IN
A
SSIGNMENTS FOR
32-
PIN
TSOP
TABLE 1: P
IN
D
ESCRIPTION
Symbol
A
MS1
-A
0
WE#
ROMCS#
DQ
7
-DQ
0
V
DD
V
SS
Pin Name
Address Inputs, for ROM: A
MS
= A
18
, for RAM: A
MS
=A
16
for SST30VR041
A
14
for SST30VR043
Write Enable Input
ROM Enable Input
Data Input/Output
Power Supply
Ground
T1.2 381
OE#/RAMCS# Output Enable/RAM Enable Input
1. A
MS
= Most significant address
©2001 Silicon Storage Technology, Inc.
S71134-02-000 4/01
381
2
4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR041 / SST30VR043
Preliminary Specifications
Absolute Maximum Stress Ratings
(Applied conditions greater than those listed under “Absolute Maximum
Stress Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation
of the device at these conditions or conditions greater than those defined in the operational sections of this data
sheet is not implied. Exposure to absolute maximum stress rating conditions may affect device reliability.)
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -20°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65°C to +150°C
Voltage on Any Pin Relative to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to V
DD
+ 0.5V
Voltage on V
DD
Supply Relative to V
SS
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 4.0V
Power Dissipation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0W
Soldering Temperature (10 Seconds Lead Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
O
PERATING
R
ANGE
Range
Commercial
Extended
Ambient Temp
0°C to +70°C
V
DD
2.7-3.3V
2.7-3.3V
-20°C to +85°C
OF
AC C
ONDITIONS
T
EST
Input Pulse Level
. . . . . . . . . . . . . . . . . . . . 0-V
DD
Input & Output Timing Reference Levels
. . . V
DD
/2
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . 5 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . C
L
= 30 pF for 70 ns
Output Load . . . . . . . . . . . . . . . . . . . . . . . . . C
L
= 100 pF for 150 ns
TABLE 2: R
ECOMMENDED
DC O
PERATING
C
ONDITIONS
Symbol
V
DD
V
SS
V
IH
V
IL
Parameter
Supply Voltage
Ground
Input High Voltage
Input Low Voltage
Min
2.7
0
2.4
-0.3
Max
3.3
0
V
DD
+ 0.5
0.3
Units
V
V
V
V
T2.0 381
TABLE 3: DC O
PERATING
C
HARACTERISTICS
V
DD
= 3.0±0.3V
Symbol
I
DD1
I
DD2
I
SB
I
LI
I
LO
V
OL
V
OH
Parameter
ROM Operating Supply Current
RAM Operating Supply Current
Standby V
DD
Current
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
2.2
-1
-1
Min
Max
4.0+1.1(f)
1
2.5+1(f)
1
10
1
1
0.4
Units
mA
mA
µA
µA
µA
V
V
Test Conditions
ROMCS# = V
IL
, RAMCS# = V
IH
,
V
IN
= V
IH
or V
IL,
I
I/O
= Opens
ROMCS# = V
IH
, RAMCS# = V
IL
, I
I/O
= Opens
ROMCS#
≥
V
DD
-0.2V, RAMCS#
≥
V
DD
-0.2V
V
IN
≥
V
DD
-0.2V or V
IN
≤
0.2V
V
IN
= V
SS
to V
DD
ROMCS# = RAMCS# = V
IH
or OE# = V
IH
or
WE# = V
IL
, V
I/O
= V
SS
to V
DD
I
OL
= 1.0 mA
I
OH
= -0.5 mA
T3.4 381
1. f = Frequency of operation (MHz) = 1/cycle time
©2001 Silicon Storage Technology, Inc.
S71134-02-000 4/01
381
3
4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR041 / SST30VR043
Preliminary Specifications
TABLE 4: C
APACITANCE
Parameter
C
I/O
1
(Ta = 25°C, f=1 Mhz)
Description
I/O Pin Capacitance
Input Capacitance
Test Condition
V
I/O
= 0V
V
IN
= 0V
Maximum
8 pF
6 pF
T4.1 381
C
IN1
1. This parameter is measured only for initial qualification and after a design or process change that could affect this parameter.
VIHT
INPUT
VIT
REFERENCE POINTS
VOT
OUTPUT
VILT
381 ILL F07.0
AC test inputs are driven at V
IHT
(0.9 V
DD
) for a logic “1” and V
ILT
(0.1 V
DD
) for a logic “0”. Measurement reference points
for inputs and outputs are V
IT
(0.5 V
DD
) and V
OT
(0.5 V
DD
). Input rise and fall times (10%
↔
90%) are <5 ns.
Note:
V
IT
- V
INPUT
Test
V
OT
- V
OUTPUT
Test
V
IHT
- V
INPUT
HIGH Test
V
ILT
- V
INPUT
LOW Test
FIGURE 2: AC I
NPUT
/O
UTPUT
R
EFERENCE
W
AVEFORMS
TO TESTER
TO DUT
CL
381 ILL F08.0
FIGURE 3: A T
EST
L
OAD
E
XAMPLE
©2001 Silicon Storage Technology, Inc.
S71134-02-000 4/01
381
4
4 Mbit ROM + 1 Mbit / 256 Kbit SRAM ROM/RAM Combo
SST30VR041 / SST30VR043
Preliminary Specifications
AC CHARACTERISTICS
I. ROM Operation
TABLE 5: R
EAD
C
YCLE
T
IMING
P
ARAMETERS
Symbol
T
RC
T
AA
T
CO
T
OE
T
LZ
T
OLZ
T
HZ
T
OHZ
T
OH
Parameter
Read Cycle Time
Address Access Time
Chip Select to Output
Output Enable to Valid Output
Chip Select to Low-Z Output
Output Enable to Low-Z Output
Chip Disable to High-Z Output
Output Disable to High-Z Output
Output Hold from Address Change
10
0
0
25
25
15
V
DD
= 3.0V±0.3
SST30VR041-70
Min
70
70
70
35
0
0
30
30
Max
SST30VR041/043-150
Min
150
150
150
70
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
T5.2 381
TRC
Address
TAA
TOH
Data Out
Previous Data Valid
Data Valid
381 ILL F02.0
FIGURE 4: ROM R
EAD
C
YCLE
T
IMING
D
IAGRAM
(A
DDRESS
C
ONTROLLED
) (ROMCS# = OE# = V
IL
)
©2001 Silicon Storage Technology, Inc.
S71134-02-000 4/01
381
5
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