EN25B32
EN25B32
32 Mbit Serial Flash Memory with Boot and Parameter Sectors
FEATURES
•
Single power supply operation
- Full voltage range: 2.7-3.6 volt
•
32 M-bit Serial Flash
- 32 M-bit/4096 K-byte/16384 pages
- 256 bytes per programmable page
•
High performance
- 100MHz clock rate
•
Low power consumption
- 5 mA typical active current
- 1
μA
typical power down current
•
Flexible Sector Architecture:
- Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one
32-Kbyte, and sixty three 64-Kbyte sectors
•
Software and Hardware Write Protection:
- Write Protect all or portion of memory via
software
- Enable/Disable protection with WP# pin
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High performance program/erase speed
Byte program time: 7µs typical
Page program time: 1.5ms typical
Sector erase time: 300 to 800ms typical
Chip erase time: 25 Seconds typical
•
Lockable 512byte OTP security sector
•
Minimum 100K endurance cycle
•
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Package Options
16 pins SOP 300mil body width
8 pins SOP 200mil body width
8 contact VDFN
8 pins PDIP
All Pb-free packages are RoHS compliant
•
Commercial and industrial temperature
Range
GENERAL DESCRIPTION
The EN25B32 is a 32M-bit (4096K-byte) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to
256 bytes at a time, using the Page Program instruction.
The EN25B32 has sixty eight sectors including sixty three sectors of 64KB, one sector of 32KB, one
sector of 16KB, one sector of 8KB and two sectors of 4KB. This device is designed to allow either single
Sector at a time or full chip erase operation. The EN25B32 can protect boot code stored in the small
sectors for either bottom or top boot configurations. The device can sustain a minimum of 100K
program/erase cycles on each sector.
This Data Sheet may be revised by subsequent versions
1
or modifications due to changes in technical specifications.
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/06/21
EN25B32
Figure.1 CONNECTION DIAGRAMS
8 - LEAD SOP / PDIP
8 - CONTACT VDFN
16 - LEAD SOP
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
2
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/06/21
EN25B32
Figure 2. BLOCK DIAGRAM
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
3
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/06/21
EN25B32
SIGNAL DESCRIPTION
Serial Data Input (DI)
The SPI Serial Data Input (DI) pin provides a means for instructions, addresses and data to be
serially written to (shifted into) the device. Data is latched on the rising edge of the Serial Clock (CLK)
input pin.
Serial Data Output (DO)
The SPI Serial Data Output (DO) pin provides a means for data and status to be serially read from (shifted
out of) the device. Data is shifted out on the falling edge of the Serial Clock (CLK) input pin.
Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations. ("See SPI
Mode")
Chip Select (CS#)
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high the device is
deselected and the Serial Data Output (DO) pin is at high impedance. When deselected, the devices
power consumption will be at standby levels unless an internal erase, program or status register cycle is
in progress. When CS# is brought low the device will be selected, power consumption will increase to
active levels and instructions can be written to and data read from the device. After power-up, CS# must
transition from high to low before a new instruction will be accepted.
Hold (HOLD#)
The HOLD pin allows the device to be paused while it is actively selected. When HOLD is brought low,
while CS# is low, the DO pin will be at high impedance and signals on the DI and CLK pins will be ignored
(don’t care). The hold function can be useful when multiple devices are sharing the same SPI signals.
Write Protect (WP#)
The Write Protect (WP#) pin can be used to prevent the Status Register from being written. Used in
conjunction with the Status Register’s Block Protect (BP0, BP1and BP2) bits and Status Register Protect
(SRP) bits, a portion or the entire memory array can be hardware protected.
Table 1. PIN Names
Symbol
CLK
DI
DO
CS#
WP#
HOLD#
Vcc
Vss
Pin Name
Serial Clock Input
Serial Data Input
Serial Data Output
Chip Enable
Write Protect
Hold Input
Supply Voltage (2.7-3.6V)
Ground
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
4
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
Rev. C, Issue Date: 2007/06/21
EN25B32
MEMORY ORGANIZATION
The memory is organized as:
4,194,304 bytes
Flexible Sector Architecture
Two 4-Kbyte, one 8-Kbyte, one 16-Kbyte,one 32-Kbyte, and sixty three 64-Kbyte sectors
Bottom or top boot configurations
16384
pages (256 bytes each)
Each page can be individually programmed (bits are programmed from 1 to 0). The device is Sector or
Bulk Erasable but not Page Erasable.
Table 2a.
Bottom Boot Block Sector Architecture
Sector
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
SECTOR SIZE (KByte)
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
64
5
Address range
3F0000h – 3FFFFFh
3E0000h – 3EFFFFh
3D0000h – 3DFFFFh
3C0000h – 3CFFFFh
3B0000h – 3BFFFFh
3A0000h – 3AFFFFh
390000h – 39FFFFh
380000h – 38FFFFh
370000h – 37FFFFh
360000h – 36FFFFh
350000h – 35FFFFh
340000h – 34FFFFh
330000h – 33FFFFh
320000h – 32FFFFh
310000h – 31FFFFh
300000h – 30FFFFh
2F0000h – 2FFFFFh
2E0000h – 2EFFFFh
2D0000h – 2DFFFFh
2C0000h – 2CFFFFh
2B0000h – 2BFFFFh
2A0000h – 2AFFFFh
290000h – 29FFFFh
280000h – 28FFFFh
270000h – 27FFFFh
260000h – 26FFFFh
250000h – 25FFFFh
240000h – 24FFFFh
230000h – 23FFFFh
220000h – 22FFFFh
210000h – 21FFFFh
200000h – 20FFFFh
1F0000h – 1FFFFFh
1E0000h – 1EFFFFh
1D0000h – 1DFFFFh
1C0000h – 1CFFFFh
©2004 Eon Silicon Solution, Inc., www.essi.com.tw
This Data Sheet may be revised by subsequent versions
or modifications due to changes in technical specifications.
Rev. C, Issue Date: 2007/06/21
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