OXMPCI952-LQAG datasheet, PDF - EEWORLD Datasheet

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OXMPCI952-LQAG: Descriptionintegrated high performance dual uarts, 8-bit local bus/parallel port. 3.3v pci/minipci interface.; File Size657KB，108 Pages; ManufacturerOxford; Websitehttp://www.oxsemi.com

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OXMPCI952-LQAG Overview

integrated high performance dual uarts, 8-bit local bus/parallel port. 3.3v pci/minipci interface.

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OXmPCI952 DATA SHEET

EATURES

•

Dual 16C950 High performance UART channels

8-bit Pass-through Local Bus (PCI

Bridge)

IEEE1284 Compliant SPP/EPP/ECP parallel port

(with

external transceiver)

Efficient 32-bit, 33MHz, Multi-function target-only PCI

controller, fully compliant to PCI Local Bus specification 3.0,

and PCI Power Management Specification 1.1

PCI and miniPCI Modes

(with CLKRUN# and PME#

generation in the D3cold state, in miniPCI mode)

UARTs fully software compatible with 16C550-type devices.

UART operation up to 60 MHz via external clock source. Up

to 20MHz with the crystal oscillator.

Baud rates up to 60Mbps in external 1x clock mode and

15Mbps in asynchronous mode.

128-byte deep FIFO per transmitter and receiver

Flexible clock prescaler, from 1 to 31.875

Automated in-band flow control using programmable

Xon/Xoff in both directions

Automated out-of-band flow control using CTS#/RTS#

and/or DSR#/DTR#

•

Integrated High Performance Dual UARTs,

8-bit Local Bus/Parallel Port.

3.3v PCI/miniPCI interface

Arbitrary trigger levels for receiver and transmitter FIFO

interrupts and automatic in-band and out-of-band flow

control

Infra-red (IrDA) receiver and transmitter operation

9-bit data framing, as well as 5,6,7 and 8 bits

Detection of bad data in the receiver FIFO

Global Interrupt Status and readable FIFO levels to facilitate

implementation of efficient device drivers.

Local registers to provide status/control of device functions.

11 multi-purpose I/O pins, which can be configured as input

interrupt pins or ‘wake-up’.

Auto-detection of a wide range of Microwire

compatible

EEPROMs, to configure device parameters.

Function access, to pre-configure each function prior to

handover to generic device drivers.

Operation via IO or memory mapping.

3.3V operation (5v tolerance on selected I/Os)

Extended Operating Temp. Range : -40C to 105C

160-pin LQFP/176-pin BGA package

ESCRIPTION

The OXmPCI952 is a single chip solution for PCI and mini-

PCI based serial and parallel expansion add-in cards. It is

a dual function PCI device, where function 0 offers two

ultra-high performance OX16C950 UARTs, and function 1

is configurable either as an 8-bit Local Bus or a bi-

directional parallel port.

Each UART channel in the OXmPCI952 is the fastest

available PC-compatible UART, offering data rates up to

15Mbps and 128-byte deep transmitter and receiver FIFOs.

The deep FIFOs reduce CPU overhead and allow

utilisation of higher data rates. Each UART channel is

software compatible with the widely used industry-standard

16C550 devices (and compatibles), as well as the

OX16C95x family of high performance UARTs. In addition

to increased performance and FIFO size, the UARTs also

provide the full set of OX16C95x enhanced features

including automated in-band flow control, readable FIFO

levels etc.

To enhance device driver efficiency and reduce interrupt

latency, internal UARTs have multi-port features such as

shadowed FIFO fill levels, a global interrupt source register

and Good-Data Status, readable in four adjacent DWORD

registers visible to logical functions in I/O space and

memory space.

Expansion of serial cards beyond two channels is possible

using the 8-bit pass-through Local Bus function. The

addressable space can be increased up to 256 bytes, and

divided into four chip-select regions. This flexible

expansion scheme caters for cards with up to 18 serial

ports using external 16C950, 16C952, 16C954 or

compatible devices, or composite applications such as

combined serial and parallel port expansion cards.

The parallel port is an IEEE 1284 compliant SPP/EPP/

ECP parallel port that fully supports the existing Centronics

interface. The parallel port can be enabled in place of the

Local Bus. An

external bus transceiver is required for 5V

parallel port operation.

The configuration register values are programmed using an

external Microwire

compatible serial EEPROM. This

EEPROM can also be used to provide

function access,

pre-configure each UART into enhanced modes or pre-

configure devices on the local bus/parallel port, prior to any

PCI configuration accesses and before control is handed to

(generic) device drivers.

Oxford Semiconductor Ltd.

External—Free Release

25 Milton Park, Abingdon, Oxon, OX14 4SH, UK

Tel: +44 (0)1235 824900

Fax: +44(0)1235 821141

Oxford Semiconductor 2005

OXmPCI952 DataSheet DS-0020 – June 2005

OXFORD SEMICONDUCTOR LTD.

OXmPCI952

ABLE OF

ONTENTS

5.1

5.2

5.2.1

5.3

5.3.1

5.3.2

5.3.3

5.4

5.4.1

5.4.2

5.4.3

5.4.4

5.4.5

5.4.6

5.4.7

5.4.8

5.5

5.6

5.6.1

5.6.2

5.7

5.8

2.1

2.2

3.1

3.2

BLOCK DIAGRAM ................................................................................................................................ 8

PIN INFORMATION—160-PIN LQFP .................................................................................................... 9

PINOUTS............................................................................................................................................................................. 9

PIN DESCRIPTIONS......................................................................................................................................................... 10

PINOUTS........................................................................................................................................................................... 16

PIN DESCRIPTIONS......................................................................................................................................................... 17

PIN INFORMATION—176-PIN BGA.................................................................................................... 16

CONFIGURATION & OPERATION ..................................................................................................... 22

PCI TARGET CONTROLLER.............................................................................................................. 23

OPERATION ..................................................................................................................................................................... 23

CONFIGURATION SPACE ............................................................................................................................................... 23

PCI CONFIGURATION SPACE REGISTER MAP........................................................................................................ 24

ACCESSING LOGICAL FUNCTIONS .............................................................................................................................. 26

PCI ACCESS TO INTERNAL UARTS........................................................................................................................... 26

PCI ACCESS TO 8-BIT LOCAL BUS............................................................................................................................ 27

PCI ACCESS TO PARALLEL PORT ............................................................................................................................ 28

ACCESSING LOCAL CONFIGURATION REGISTERS................................................................................................... 29

LOCAL CONFIGURATION AND CONTROL REGISTER ‘LCC’ (OFFSET 0X00) ........................................................ 29

MULTI-PURPOSE I/O CONFIGURATION REGISTER ‘MIC’ (OFFSET 0X04) ............................................................ 30

LOCAL BUS TIMING PARAMETER REGISTER 1 ‘LT1’ (OFFSET 0X08): .................................................................. 32

LOCAL BUS TIMING PARAMETER REGISTER 2 ‘LT2’ (OFFSET 0X0C): ................................................................. 33

UART RECEIVER FIFO LEVELS ‘URL’ (OFFSET 0X10)............................................................................................. 35

UART TRANSMITTER FIFO LEVELS ‘UTL’ (OFFSET 0X14)...................................................................................... 35

UART INTERRUPT SOURCE REGISTER ‘UIS’ (OFFSET 0X18)............................................................................... 35

GLOBAL INTERRUPT STATUS AND CONTROL REGISTER ‘GIS’ (OFFSET 0X1C) ................................................ 36

PCI INTERRUPTS............................................................................................................................................................. 38

POWER MANAGEMENT .................................................................................................................................................. 39

POWER MANAGEMENT OF FUNCTION 0 ................................................................................................................. 39

POWER MANAGEMENT OF FUNCTION 1 ................................................................................................................. 40

MINIPCI SUPPORT........................................................................................................................................................... 42

DEVICE DRIVERS ............................................................................................................................................................ 46

6.1

6.1.1

6.1.2

6.1.3

6.1.4

6.1.5

6.1.6

6.2

6.3

6.3.1

6.3.2

6.4

6.4.1

6.5

6.5.1

6.5.2

6.5.3

INTERNAL OX16C950 UARTS ........................................................................................................... 47

OPERATION – MODE SELECTION ................................................................................................................................. 47

450 MODE..................................................................................................................................................................... 47

550 MODE..................................................................................................................................................................... 47

EXTENDED 550 MODE ................................................................................................................................................ 47

750 MODE..................................................................................................................................................................... 47

650 MODE..................................................................................................................................................................... 47

950 MODE..................................................................................................................................................................... 48

REGISTER DESCRIPTION TABLES ............................................................................................................................... 49

RESET CONFIGURATION ............................................................................................................................................... 53

HARDWARE RESET .................................................................................................................................................... 53

SOFTWARE RESET ..................................................................................................................................................... 53

TRANSMITTER AND RECEIVER FIFOS ......................................................................................................................... 54

FIFO CONTROL REGISTER ‘FCR’ .............................................................................................................................. 54

LINE CONTROL & STATUS............................................................................................................................................. 55

FALSE START BIT DETECTION.................................................................................................................................. 55

LINE CONTROL REGISTER ‘LCR’............................................................................................................................... 55

LINE STATUS REGISTER ‘LSR’ .................................................................................................................................. 56

Page 3

DS-0020 Jun 05

OXFORD SEMICONDUCTOR LTD.

OXmPCI952

6.6

INTERRUPTS & SLEEP MODE........................................................................................................................................ 57

6.6.1

INTERRUPT ENABLE REGISTER ‘IER’....................................................................................................................... 57

6.6.2

INTERRUPT STATUS REGISTER ‘ISR’....................................................................................................................... 58

6.6.3

INTERRUPT DESCRIPTION ........................................................................................................................................ 58

6.6.4

SLEEP MODE ............................................................................................................................................................... 59

6.7

MODEM INTERFACE ....................................................................................................................................................... 59

6.7.1

MODEM CONTROL REGISTER ‘MCR’........................................................................................................................ 59

6.7.2

MODEM STATUS REGISTER ‘MSR’ ........................................................................................................................... 60

6.8

OTHER STANDARD REGISTERS ................................................................................................................................... 60

6.8.1

DIVISOR LATCH REGISTERS ‘DLL & DLM’................................................................................................................ 60

6.8.2

SCRATCH PAD REGISTER ‘SPR’ ............................................................................................................................... 60

6.9

AUTOMATIC FLOW CONTROL....................................................................................................................................... 61

6.9.1

ENHANCED FEATURES REGISTER ‘EFR’................................................................................................................. 61

6.9.2

SPECIAL CHARACTER DETECTION .......................................................................................................................... 62

6.9.3

AUTOMATIC IN-BAND FLOW CONTROL ................................................................................................................... 62

6.9.4

AUTOMATIC OUT-OF-BAND FLOW CONTROL ......................................................................................................... 62

6.10 BAUD RATE GENERATION............................................................................................................................................. 63

6.10.1

GENERAL OPERATION ............................................................................................................................................... 63

6.10.2

CLOCK PRESCALER REGISTER ‘CPR’...................................................................................................................... 63

6.10.3

TIMES CLOCK REGISTER ‘TCR’................................................................................................................................. 63

6.10.4

EXTERNAL 1X CLOCK MODE..................................................................................................................................... 65

6.10.5

CRYSTAL OSCILLATOR CIRCUIT .............................................................................................................................. 65

6.11 ADDITIONAL FEATURES ................................................................................................................................................ 65

6.11.1

ADDITIONAL STATUS REGISTER ‘ASR’ .................................................................................................................... 65

6.11.2

FIFO FILL LEVELS ‘TFL & RFL’ ................................................................................................................................... 66

6.11.3

ADDITIONAL CONTROL REGISTER ‘ACR’................................................................................................................. 66

6.11.4

TRANSMITTER TRIGGER LEVEL ‘TTL’ ...................................................................................................................... 67

6.11.5

RECEIVER INTERRUPT. TRIGGER LEVEL ‘RTL’ ...................................................................................................... 67

6.11.6

FLOW CONTROL LEVELS ‘FCL’ & ‘FCH’ .................................................................................................................... 67

6.11.7

DEVICE IDENTIFICATION REGISTERS...................................................................................................................... 67

6.11.8

CLOCK SELECT REGISTER ‘CKS’.............................................................................................................................. 68

6.11.9

NINE-BIT MODE REGISTER ‘NMR’ ............................................................................................................................. 68

6.11.10 MODEM DISABLE MASK ‘MDM’ .................................................................................................................................. 69

6.11.11 READABLE FCR ‘RFC’................................................................................................................................................. 69

6.11.12 GOOD-DATA STATUS REGISTER ‘GDS’.................................................................................................................... 69

6.11.13 PORT INDEX REGISTER ‘PIX’..................................................................................................................................... 69

6.11.14 CLOCK ALTERATION REGISTER ‘CKA’ ..................................................................................................................... 70

7.1

7.2

7.3

LOCAL BUS ........................................................................................................................................ 71

OVERVIEW ....................................................................................................................................................................... 71

OPERATION ..................................................................................................................................................................... 71

CONFIGURATION & PROGRAMMING............................................................................................................................ 72

OPERATION AND MODE SELECTION ........................................................................................................................... 73

SPP MODE ................................................................................................................................................................... 73

PS2 MODE.................................................................................................................................................................... 73

EPP MODE ................................................................................................................................................................... 73

ECP MODE ................................................................................................................................................................... 73

PARALLEL PORT INTERRUPT ....................................................................................................................................... 74

REGISTER DESCRIPTION............................................................................................................................................... 75

PARALLEL PORT DATA REGISTER ‘PDR’ ................................................................................................................. 75

ECP FIFO ADDRESS / RLE ......................................................................................................................................... 75

DEVICE STATUS REGISTER ‘DSR’ ............................................................................................................................ 75

DEVICE CONTROL REGISTER ‘DCR’......................................................................................................................... 76

EPP ADDRESS REGISTER ‘EPPA’ ............................................................................................................................. 76

EPP DATA REGISTERS ‘EPPD1-4’ ............................................................................................................................. 76

Page 4

8.1

8.1.1

8.1.2

8.1.3

8.1.4

8.2

8.3

8.3.1

8.3.2

8.3.3

8.3.4

8.3.5

8.3.6

BIDIRECTIONAL PARALLEL PORT .................................................................................................. 73

DS-0020 Jun 05

OXFORD SEMICONDUCTOR LTD.

8.3.7

8.3.8

8.3.9

8.3.10

8.3.11

OXmPCI952

ECP DATA FIFO ........................................................................................................................................................... 76

TEST FIFO .................................................................................................................................................................... 76

CONFIGURATION A REGISTER ................................................................................................................................. 76

CONFIGURATION B REGISTER ................................................................................................................................. 76

EXTENDED CONTROL REGISTER ‘ECR’................................................................................................................... 77

SPECIFICATION ............................................................................................................................................................... 78

ZONE 0: HEADER ........................................................................................................................................................ 79

ZONE 1: LOCAL CONFIGURATION REGISTERS....................................................................................................... 80

ZONE 2: IDENTIFICATION REGISTERS ..................................................................................................................... 81

ZONE 3: PCI CONFIGURATION REGISTERS ............................................................................................................ 81

ZONE 4 : POWER MANAGEMENT DATA

(AND DATA_SCALE ZONE) ............................................................. 82

ZONE 5 : FUNCTION ACCESS .................................................................................................................................... 82

MINIMUM PROGRAMMING REQUIREMENTS. .......................................................................................................... 83

9.1

9.1.1

9.1.2

9.1.3

9.1.4

9.1.5

9.1.6

9.1.7

SERIAL EEPROM................................................................................................................................ 78

10.1

11.1

11.2

11.3

OPERATING CONDITIONS ............................................................................................................. 84

DC ELECTRICAL CHARACTERISTICS .......................................................................................................................... 84

AC ELECTRICAL CHARACTERISTICS.......................................................................................... 86

PCI BUS ............................................................................................................................................................................ 86

LOCAL BUS...................................................................................................................................................................... 86

SERIAL PORTS ................................................................................................................................................................ 88

13.1

13.2

TIMING WAVEFORMS..................................................................................................................... 89

PACKAGE INFORMATION............................................................................................................ 104

160-PIN LQFP PACKAGE .............................................................................................................................................. 104

176-PIN BGA PACKAGE................................................................................................................................................ 105

ORDERING INFORMATION .......................................................................................................... 106

DS-0020 Jun 05

Page 5

OXMPCI952-LQAG Related Products

	OXMPCI952-LQAG	OXMPCI952-VBAG	OXMPCI952	OXMPCI952-LQ-A
Description	integrated high performance dual uarts, 8-bit local bus/parallel port. 3.3v pci/minipci interface.	integrated high performance dual uarts, 8-bit local bus/parallel port. 3.3v pci/minipci interface.	integrated high performance dual uarts, 8-bit local bus/parallel port. 3.3v pci/minipci interface.	integrated high performance dual uarts, 8-bit local bus/parallel port. 3.3v pci/minipci interface.

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