ARM610
Data Sheet
Zarlink Part Number: P610ARM-B/KG/FPNR
P610ARM-B/KW/FPNR
Notes
1)
2)
The original P610ARM/KG/FPNR is obsolete
This datasheet includes the performance data previously supplied in supplement
MS4397 - Jan 1996
DS3554
ISSUE 3.2
October 2001
Manufactured under licence from Advanced RISC Machines Ltd
ARM and the ARM logo are trademarks of Advanced RISC Machines Ltd
© Advanced RISC Machines Ltd 1999
Preface
The ARM610 is a general purpose 32-bit microprocessor with
4
kByte cache, write buffer and Memory
Management Unit (MMU) combined in a single chip. The ARM610 offers high level RISC performance yet
its fully static design ensures minimal power consumption, making it ideal for portable, low-cost systems.
The innovative MMU supports a conventional two-level page-table structure and a number of extensions
which make it ideal for embedded control, UNIX and Object Oriented systems. This results in a high
instruction throughput and impressive real-time interrupt response from a small and cost-effective chip.
Applications
The ARM610 is ideally suited to those applications requiring RISC performance from a compact, power
efficient processor. These include:
•
•
•
•
•
•
Personal computer devices eg.PDAs
High-performance real-time control systems
Portable telecommunications
Data communications equipment
Consumer products
Automotive
Feature Summary
•
High performance RISC
25 MIPS sustained @ 33 MHz
(33 MIPS peak)
Address
Bus
JTAG
4Kbyte
Cache
MMU
ARM6
CPU
•
Fast sub microsecond interrupt response
for real-time applications
•
Memory Management Unit (MMU)
support for virtual memory systems
•
•
•
•
Excellent high-level language support
4kByte of instruction & data cache
Big and Little Endian operating modes
Write Buffer
enhancing performance
Write
Buffer
Control
•
•
IEEE 1149.1 Boundary Scan
Fully static operation, low power consumption
ideal for power sensitive applications
•
144 Thin Quad Flat Pack (TQFP) package
Preface-ii
ARM610 Data Sheet
TOC
1
Introduction
1.1
1.2
1.3
Introduction
Block Diagram
Functional Diagram
Signal Description
Introduction
Register Configuration
Operating Mode Selection
Registers
Exceptions
Reset
Contents
1-1
1-2
1-4
1-5
2
3
Signal Description
2.1
3.1
3.2
3.3
3.4
3.5
3.6
2-1
2-2
Programmer’s Model
3-1
3-2
3-2
3-3
3-3
3-6
3-10
4
Instruction Set
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10
4.11
4.12
Instruction Set Summary
The Condition Field
Branch and Branch with Link (B, BL)
Data Processing
PSR Transfer (MRS, MSR)
Multiply and Multiply-Accumulate (MUL, MLA)
Single Data Transfer (LDR, STR)
Halfword and Signed Data Transfer
Block Data Transfer (LDM, STM)
Single Data Swap (SWP)
Software Interrupt (SWI)
Coprocessor Data Operations (CDP)
4-1
4-2
4-5
4-7
4-9
4-17
4-22
4-24
4-30
4-36
4-43
4-45
4-47
ARM610 Data Sheet
Contents-1
Contents
4.13
4.14
4.15
4.16
Coprocessor Data Transfers (LDC, STC)
Coprocessor Register Transfers (MRC, MCR)
Undefined Instruction
Instruction Set Examples
Configuration
Internal Coprocessor Instructions
Registers
Introduction
Cacheable Bit - C
Updateable Bit - U
IDC Operation
IDC Validity
Read-Lock-Write
IDC Enable/Disable and Reset
Introduction
Bufferable Bit
Write Buffer Operation
Overview
Memory Management Unit (MMU)
MMU Program Accessible Registers
Address Translation
Translation Process
Level One Descriptor
Page Table Descriptor
Section Descriptor
Translating Section References
Level Two Descriptor
Translating Small Page References
Translating Large Page References
MMU Faults and CPU Aborts
Fault Address and Fault Status Registers (FAR and FSR)
Domain Access Control
Fault Checking Sequence
External Aborts
Interaction of the MMU, IDC and Write Buffer
Effect of Reset
4-49
4-53
4-55
4-56
5
Configuration
5.1
5.2
5.3
5-1
5-2
5-2
5-2
6
Instruction and Data Cache (IDC)
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6-1
6-2
6-2
6-2
6-2
6-3
6-3
6-4
7
Write Buffer (WB)
7.1
7.2
7.3
7-1
7-2
7-2
7-2
8
9
Coprocessors
8.1
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
9.16
9.17
9.18
8-1
8-2
Memory Management Unit
9-1
9-2
9-2
9-3
9-4
9-5
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-11
9-13
9-14
9-16
9-17
9-18
10
Bus interface
10.1 Introduction
10.2 ARM610 Cycle Speed
10-1
10-2
10-2
Contents-2
ARM610 Data Sheet
Contents
10.3
10.4
10.5
10.6
10.7
10.8
10.9
Cycle Types
Memory Access
Read/Write
Byte/Word
Maximum Sequential Length
Memory Access Types
ARM610 Cycle Type Summary
Introduction
Overview
Reset
Pullup Resistors
Instruction Register
Public Instructions
Test Data Registers
Boundary-Scan Interface Signals
10-2
10-2
10-3
10-3
10-3
10-5
10-9
11
Boundary-Scan Test Interface
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11-1
11-2
11-2
11-3
11-3
11-3
11-3
11-7
11-10
12
DC Parameters
12.1 Absolute Maximum Ratings
12.2 DC Operating Conditions
12.3 DC Characteristics
12-1
12-2
12-2
12-3
13
AC Parameters
13.1 Test Conditions
13.2 Relationship between FCLK and MCLK
13.3 Main Bus Signals
13-1
13-2
13-2
13-4
14
15
Physical details
14.1 Physical Details
14-1
14-2
Pinout
15.1 Pinout
15-1
15-2
Backward Compatibility
Backward Compatibility
A-1
A-2
ARM610 Data Sheet
Contents-3
DSP and ARM Processors
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