White Electronic Designs
512MB – 64Mx64 SDRAM UNBUFFERED
FEATURES
PC100 and PC133 compatible
Burst Mode Operation
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the
positive edge of the system clock
Programmable Burst Lengths: 1, 2, 4, 8 or Full
Page
3.3V ± 0.3V Power Supply
144 Pin SO-DIMM JEDEC
•
Package height option:
JD1: 31.75 mm (1.25”)
WED3DG6466V-D1
-JD1
DESCRIPTION
The WED3DG6466V is a 64Mx64 synchronous DRAM
module which consists of eight 64Mx8 SDRAM components
in TSOP II package, and one 2K EEPROM in an 8 pin
TSSOP package for Serial Presence Detect which
are mounted on a 144 pin SO-DIMM multilayer FR4
Substrate.
* This product is subject to change without notice.
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PINOUT
PIN
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
FRONT
V
SS
DQ0
DQ1
DQ2
DQ3
V
CC
DQ4
DQ5
DQ6
DQ7
V
SS
DQMB0
DQMB1
V
CC
A0
A1
A2
V
SS
DQ8
DQ9
DQ10
DQ11
V
CC
DQ12
PIN
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
BACK
V
SS
DQ32
DQ33
DQ34
DQ35
V
CC
DQ36
DQ37
DQ38
DQ39
V
SS
DQMB4
DQMB5
V
CC
A3
A4
A5
V
SS
DQ40
DQ41
DQ42
DQ43
V
CC
DQ44
PIN
49
51
53
55
57
59
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
FRONT
DQ13
DQ14
DQ15
V
SS
NC
NC
CKL0
V
CC
RAS#
WE#
CS0#
NC
NC
V
SS
NC
NC
V
CC
DQ16
DQ17
DQ18
DQ19
V
SS
DQ20
DQ21
PIN
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
BACK
DQ45
DQ46
DQ47
V
SS
NC
NC
CKE0
V
CC
CAS#
NC
A12
NC
CK1
V
SS
NC
NC
V
CC
DQ48
DQ49
DQ50
DQ51
V
SS
DQ52
DQ53
PIN
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
BACK
DQ22
DQ23
V
CC
A6
A8
V
SS
A9
A10
V
CC
DQMB2
DQMB3
V
SS
DQ24
DQ25
DQ26
DQ27
V
CC
DQ28
DQ29
DQ30
DQ31
V
SS
SDA
V
CC
PIN
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
BACK
DQ54
DQ55
V
CC
A7
BA0
V
SS
BA1
A11
V
CC
DQMB6
DQMB7
V
SS
DQ56
DQ57
DQ58
DQ59
V
CC
DQ60
DQ61
DQ62
DQ63
V
SS
SCL
V
CC
PIN NAMES
A0 – A12
BA0-1
DQ0-63
CK0, CK1
CKE0
CS0
RAS#
CAS#
WE#
DQMB0-7
V
CC
V
SS
SDA
SCL
DNU
NC
Address Input (Multiplexed)
Select Bank
Data Input/Output
Clock Input
Clock Enable Input
Chip Select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
Serial Data I/O
Serial Clock
Do Not Use
No Connect
July 2005
Rev. 3
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
FUNCTIONAL BLOCK DIAGRAM
WE#
S0#
DQMB0
DQM
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WE
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQMB4
DQM
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WED3DG6466V-D1
-JD1
WE
D0
D4
DQMB1
DQM
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WE
DQMB5
DQM
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WE
D1
D5
DQMB2
DQM
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WE
DQMB6
DQM
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WE
D2
D6
DQMB3
DQM
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WE
DQMB7
DQM
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
S
WE
D3
D7
NOTE: DQ writing may differ than described in this drawing,
however DQ/DQMB/CKE/S relationships must be
maintained as shown.
*CLOCK WIRING
CLOCK
INPUT
*CK0
*CK1
SDRAMS
4 - SDRAMS
4 - SDRAMS
RAS#
CAS#
CKE0
RAS#: SDRAM D0-D7
CAS#: SDRAM D0-D7
CKE: SDRAM D0-D7
*Wire per Clock Loading Table/Wiring Diagrams
BA0-BA1
A0-A12
BA0-BA1: SDRAM D0-D7
A0-A12: SDRAM D0-D7
SERIAL PD
SCL
VDD
D0-D7
A0
A1
A2
SDA
VSS
D0-D7
July 2005
Rev. 3
2
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
ABSOLUTE MAXIMUM RATINGS
Parameter
Voltage on any pin relative to V
SS
Voltage on V
CC
supply relative to V
SS
Storage Temperature
Power Dissipation
Short Circuit Current
Symbol
V
IN
, V
OUT
V
CC
, V
CCQ
T
STG
P
D
I
OS
WED3DG6466V-D1
-JD1
Value
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
9
50
Units
V
V
°C
W
mA
Note: Permanent device damage may occur if “ABSOLUTE MAXIMUM RATINGS” are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: V
SS
= 0V, 0°C
≤
T
A
≤
+70°C
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
Symbol
V
CC
V
IH
V
IL
V
OH
V
OL
I
LI
Min
3.0
2.0
-0.3
2.4
—
-10
Typ
3.3
3.0
—
—
—
—
Max
3.6
V
CCQ
+0.3
0.8
—
0.4
10
Unit
V
V
V
V
V
µA
1
2
I
OH
= -2mA
I
OL
= -2mA
3
Note
Note: 1. V
IH
(max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. V
IL
(min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ V
IN
≤ V
CCQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
T
A
= 25°C, f = 1MHz, V
CC
= 3.3V, V
REF
= 1.4V
±
200mV
Parameter
Input Capacitance (A0-A12)
Input Capacitance (RAS#,CAS#,WE#)
Input Capacitance (CKE0)
Input Capacitance (CK0)
Input Capacitance (CS0#)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data Input/Output Capacitance (DQ0-DQ63)
Symbol
C
IN1
C
IN2
C
IN3
C
IN4
C
IN5
C
IN6
C
IN7
C
OUT
Max
35
35
35
16
35
7
35
10
Unit
pF
pF
pF
pF
pF
pF
pF
pF
July 2005
Rev. 3
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
OPERATING CURRENT CHARACTERISTICS
V
CC
= 3.3V, T
A
= 0°C to +70°C
WED3DG6466V-D1
-JD1
Version
Parameter
Operating Current
(One bank active)
Precharge Standby Current
in Power Down Mode
Active Standby Current in
Non-Power Down Mode
Symbol
I
CC1
Conditions
Burst Length = 1
t
RC
≤
t
RC
(min)
I
OL
= 0mA
CKE
≤
V
IL
(max), t
CC
= 10ns
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), tcc = 10ns Input
signals are changed one time during 20ns
Io = mA
Page burst
4 Banks activated
t
CCD
= 2CK
t
RC
≥
t
RC
(min)
CKE
≤
0.2V
100/133
1080
Units
mA
Note
1
I
CC2P
I
CC3N
I
CC4
16
360
mA
mA
Operating Current (Burst mode)
1,200
mA
1
Refresh Current
Self Refresh Current
Notes:
1.
Measured with outputs open.
2.
Refresh period is 64ms.
I
CC5
I
CC6
2,280
24
mA
mA
2
July 2005
Rev. 3
4
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
White Electronic Designs
AC TIMING PARAMETERS
Speed Grade
100MHz
Symbol
t
CK
t
CH
t
CL
t
IS
t
IH
t
AC
Parameter
Clock Period
Clock High Time Rated @1.5V
Clock Low Time
Input Setup Times
Min
10
3
3
2
2
1
1
Max
WED3DG6466V-D1
-JD1
Speed Grade
133MHz
Min
7.5
2.5
2.5
1.5
1.5
0.8
0.8
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
Notes
t
OH
t
OHZ
t
CCD
t
CBD
t
CKE
t
RP
t
RAS
t
RCD
t
RRD
t
RC
t
DQD
t
DWD
t
MRD
t
ROH
t
DQZ
t
DQM
t
DPL
t
DAL
t
SB
t
SRX
t
PDE
t
CKSTP
t
REF
t
RFC
1.
2.
3.
4.
5.
6.
Address/ Command & CKE
Data
Input Hold Times
Address/Command & CKE
Data
Output Valid From Clock
CAS# Latency = 2 or 3,
LVTTL levels, Rated @ 50
pF all outputs switching
Output Hold From Clock Rated @ 50 pF (1.8 ns @ 0 pf)
Output Valid to Z
CAS to CAS Delay
CAS Bank Delay
CKE to Clock Disable
RAS Precharge Time
RAS Active Time
Activate to Command Delay (RAS to CAS Delay)
RAS to RAS Bank Activate Delay
RAS Cycle Time
DQM to Input Data Delay
Write Cmd. to Input Data Delay
Mode Register set to Active delay
Precharge to O/P in High Z
DQM to Data in High Z for read
DQM to Data mask for write
Data-in to PRE Command Period
Data-in to ACT (PRE) Command period (Auto precharge)
Power Down Mode Entry
Self Refresh Exit Time
Power Down Exit Set up Time
Clock Stop During Self Refresh or Power Down
Refresh Period
Row Refresh Cycle Time
6.0
(tco = 5.2)
3
3
1
1
1
20
50
20
20
70
0
0
3
2
0
20
5
1
10
1
200
64
80.0
75.0
10
1
200
2.7
2.7
1
1
1
20
45
20
15
67.5
0
0
3
2
0
15
5
5.4
(tco = 4.6)
1
9
7
CL
CL
1
64
ns
ns
t
CK
t
CK
t
CK
ns
ns
ns
ns
ns
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
ns
t
CK
t
CK
ns
t
CK
t
CK
ms
ns
2
3
4
5
6
Access times to be measured w/input signals of 1 V/ns edge rate, 0.8 V to 2.0 V, tCO is clock to output with no load.
CL = CAS Latency
Data Masked on the same clock
Self refresh Exit is asynchronous, requiring 10 ns to ensure initiation. Self refresh exit is complete in 10 ns + tRC.
Timing is asynchronous. If tIS is not met by rising edge of CK then CKE is assumed latched on next cycle.
If the clock is stopped during self refresh or power down, 200 clocks are required before CKE is high.
July 2005
Rev. 3
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
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