BSI
FEATURES
Very Low Power/Voltage CMOS SRAM
512K X 8 bit
DESCRIPTION
BS62LV4007
• Vcc operation voltage : 4.5V ~ 5.5V
• Very low power consumption :
Vcc = 5.0V C-grade: 68mA (@55ns) operating current
I -grade: 70mA (@55ns) operating current
C-grade: 58mA (@70ns) operating current
I -grade: 60mA (@70ns) operating current
2.0uA (Typ.) CMOS standby current
• High speed access time :
-55
55ns
-70
70ns
• Automatic power down when chip is deselected
• Fully static operation
• Data retention supply voltage as low as 1.5V
• Easy expansion with CE and OE options
• Three state outputs and TTL compatible
The BS62LV4007 is a high performance, very low power CMOS
Static Random Access Memory organized as 524,288 words by 8 bits
and operates from a range of 4.5V to 5.5V supply voltage.
Advanced CMOS technology and circuit techniques provide both high
speed and low power features with a typical CMOS standby current of
2.0uA at
5.0V/25
o
C
and maximum access time of 55ns at
5.0V/85
o
C.
Easy memory expansion is provided by an active LOW chip enable
(CE) , and active LOW output enable (OE) and three-state output
drivers.
The BS62LV4007 has an automatic power down feature, reducing the
power consumption significantly when chip is deselected.
The BS62LV4007 is available in the JEDEC standard 32L SOP, TSOP
, PDIP, TSOP II and STSOP package.
PRODUCT FAMILY
PRODUCT
FAMILY
BS62LV4007TC
BS62LV4007STC
BS62LV4007SC
BS62LV4007EC
BS62LV4007PC
BS62LV4007TI
BS62LV4007STI
BS62LV4007SI
BS62LV4007EI
BS62LV4007PI
OPERATING
TEMPERATURE
Vcc
RANGE
SPEED
( ns )
55ns :4.5~5.5V
70ns :4.5~5.5V
POWER DISSIPATION
( I
CCSB1
, Max )
STANDBY
Vcc =5.0V
Operating
( I
CC
, Max )
Vcc = 5.0V
55ns
Vcc =5.0V
70ns
PKG
TYPE
TSOP
-
32
STSOP
-
32
SOP
-
32
TSOP2
-
32
PDIP
-
32
TSOP
-
32
STSOP
-
32
SOP
-
32
TSOP2
-
32
PDIP
-
32
+0 C to +70 C
O
O
4.5V ~ 5.5V
55 / 70
30uA
68mA
58mA
-
40
O
C to +85 C
O
4.5V ~ 5.5V
55 / 70
60uA
70mA
60mA
PIN CONFIGURATIONS
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
A17
WE
A13
A8
A9
A11
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
BLOCK DIAGRAM
A13
A17
A15
A18
A16
A14
A12
A7
A6
A5
A4
•
BS62LV4007SC
BS62LV4007SI
BS62LV4007EC
BS62LV4007EI
BS62LV4007PC
BS62LV4007PI
Address
Input
Buffer
22
Row
Decoder
2048
Memory Array
2048 X 2048
2048
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
8
Data
Input
Buffer
8
Column I/O
Write Driver
Sense Amp
256
Column Decoder
16
CE
WE
OE
Vdd
GND
Control
Address Input Buffer
8
A11
A9
A8
A13
WE
A17
A15
VCC
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
BS62LV4007TC
BS62LV4007STC
BS62LV4007TI
BS62LV4007STI
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
CE
DQ7
DQ6
DQ5
DQ4
DQ3
GND
DQ2
DQ1
DQ0
A0
A1
A2
A3
Data
Output
Buffer
8
Brilliance Semiconductor, Inc
.
reserves the right to modify document contents without notice.
R0201-BS62LV4007
•
A11 A9 A8 A3 A2 A1 A0 A10
1
Revision 1.1
Jan.
2004
BSI
PIN DESCRIPTIONS
BS62LV4007
Function
These 19 address inputs select one of the 524,288 x 8-bit words in the RAM
CE is active LOW. Chip enables must be active when data read from or write to the
device. if chip enable is not active, the device is deselected and is in a standby power
mode. The DQ pins will be in the high impedance state when the device is deselected.
Name
A0-A18 Address Input
CE Chip Enable Input
WE Write Enable Input
The write enable input is active LOW and controls read and write operations. With the
chip selected, when WE is HIGH and OE is LOW, output data will be present on the
DQ pins; when WE is LOW, the data present on the DQ pins will be written into the
selected memory location.
OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is
selected and the write enable is inactive, data will be present on the DQ pins and they
will be enabled. The DQ pins will be in the high impedance state when OE is inactive.
DQ0-DQ7 Data Input/Output
Ports
Vcc
GND
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply
Ground
TRUTH TABLE
MODE
Not selected
Output Disabled
Read
Write
WE
X
H
H
L
CE
H
L
L
L
OE
X
H
L
X
I/O OPERATION
High Z
High Z
D
OUT
D
IN
Vcc CURRENT
I
CCSB
, I
CCSB1
I
CC
I
CC
I
CC
ABSOLUTE MAXIMUM RATINGS
(1)
SYMBOL
V
TERM
T
BIAS
T
STG
P
T
I
OUT
PARAMETER
Terminal Voltage
Respect to GND
with
OPERATING RANGE
UNITS
V
O
O
RATING
-0.5 to
Vcc+0.5
-40 to +85
-60 to +150
1.0
20
RANGE
Commercial
Industrial
AMBIENT
TEMPERATURE
0
O
C to +70
O
C
-40
O
C to +85
O
C
Vcc
4.5V ~ 5.5V
4.5V ~ 5.5V
Temperature Under Bias
Storage Temperature
Power Dissipation
DC Output Current
C
C
W
mA
CAPACITANCE
(1)
(TA = 25
o
C, f = 1.0 MHz)
SYMBOL
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these
or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
reliability.
C
IN
C
DQ
PARAMETER
Input
Capacitance
Input/Output
Capacitance
CONDITIONS
MAX.
UNIT
V
IN
=0V
V
I/O
=0V
6
8
pF
pF
1. This parameter is guaranteed and not 100% tested.
R0201-BS62LV4007
2
Revision 1.1
Jan.
2004
BSI
DC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
PARAMETER
NAME
V
IL
V
IH
I
IL
I
LO
V
OL
V
OH
I
CC
(5)
BS62LV4007
TEST CONDITIONS
Vcc = 5.0 V
Vcc = 5.0 V
PARAMETER
Guaranteed Input Low
Voltage
(3)
Guaranteed Input High
Voltage
(3)
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Operating Power Supply
Current
Standby Current-TTL
MIN. TYP.
-0.5
2.2
--
--
Vcc = 5.0 V
Vcc = 5.0 V
55ns
70ns
(1)
MAX.
0.8
Vcc+0.3
1
1
0.4
--
70
60
1.0
UNITS
--
--
--
--
--
--
--
V
V
uA
uA
V
V
mA
Vcc = Max, V
IN
= 0V to Vcc
Vcc = Max, CE = V
IH
, or OE = V
IH
,
V
I/O
= 0V to Vcc
Vcc = Max, I
OL
= 2.0mA
Vcc = Min, I
OH
= -1.0mA
CE = V
IL
, I
DQ
= 0mA,
F=Fmax
(2)
CE = V
IH
, I
DQ
= 0mA
CE
≧
Vcc-0.2V,
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
Vcc = 5.0 V
--
2.4
--
I
CCSB
(4)
Vcc = 5.0 V
--
--
mA
I
CCSB1
Standby Current-CMOS
Vcc = 5.0 V
--
2.0
60
uA
1. Typical characteristics are at T
A
= 25
o
C.
2. Fmax = 1/t
RC
.
3. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
4. I
cc
SB1_MAX.
is 30uA at Vcc=5.0V and T
A
=70
o
C.
5. Icc_
MAX.
is 68mA(@55ns) / 58mA(@70ns) at Vcc=5.0V and T
A
=0~70
o
C.
DATA RETENTION CHARACTERISTICS
( TA = -40 to + 85
o
C )
SYMBOL
V
DR
PARAMETER
Vcc for Data Retention
TEST CONDITIONS
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
CE
≧
Vcc - 0.2V
V
IN
≧
Vcc - 0.2V or V
IN
≦
0.2V
MIN.
1.5
TYP.
(1)
--
MAX.
--
UNITS
V
I
CCDR
t
CDR
t
R
Data Retention Current
Chip Deselect to Data
Retention Time
Operation Recovery Time
--
0
0.3
--
--
1.3
--
--
uA
ns
ns
See Retention Waveform
T
RC (2)
1. Vcc = 1.5V, T
A
= + 25
O
C
2. t
RC
= Read Cycle Time
3. I
cc
DR
_
MAX.
is 0.8uA at T
A
=70
O
C.
LOW V
CC
DATA RETENTION WAVEFORM
Vcc
V
IH
Vcc
( CE Controlled )
Data Retention Mode
V
DR
≥
1.5V
Vcc
t
CDR
CE
≥
Vcc - 0.2V
t
R
V
IH
CE
R0201-BS62LV4007
3
Revision 1.1
Jan.
2004
BSI
AC TEST CONDITIONS
(Test Load and Input/Output Reference)
BS62LV4007
KEY TO SWITCHING WAVEFORMS
Vcc / 0V
1V/ns
0.5Vcc
C
L
= 30pF+1TTL
C
L
= 100pF+1TTL
WAVEFORM
INPUTS
MUST BE
STEADY
MAY CHANGE
FROM H TO L
MAY CHANGE
FROM L TO H
DON T CARE:
ANY CHANGE
PERMITTED
DOES NOT
APPLY
OUTPUTS
MUST BE
STEADY
WILL BE
CHANGE
FROM H TO L
WILL BE
CHANGE
FROM L TO H
CHANGE :
STATE
UNKNOWN
CENTER
LINE IS HIGH
IMPEDANCE
”OFF ”STATE
Input Pulse Levels
Input Rise and Fall Times
Input and Output
Timing Reference Level
Output Load
,
AC ELECTRICAL CHARACTERISTICS
( TA = -40 to + 85
o
C )
READ CYCLE
JEDEC
PARAMETER
NAME
PARAMETER
NAME
DESCRIPTION
Read Cycle Time
Address Access Time
Chip Select Access Time
Output Enable to Output Valid
Chip Select to Output Low Z
Output Enable to Output in Low Z
Chip Deselect to Output in High Z
Output Disable to Output in High Z
Data Hold from Address Change
CYCLE TIME : 55ns
(Vcc = 4.5~5.5V)
MIN.
TYP.
MAX.
CYCLE TIME : 70ns
(Vcc = 4.5~5.5V)
MIN.
TYP. MAX.
UNIT
t
AVAX
t
AVQV
t
ELQV
t
GLQV
t
ELQX
t
GLQX
t
EHQZ
t
GHQZ
t
AXOX
t
RC
t
AA
t
ACS
t
OE
t
CLZ
t
OLZ
t
CHZ
t
OHZ
t
OH
55
--
--
--
10
10
--
--
10
--
--
--
--
--
--
--
--
--
--
55
55
30
--
--
30
25
--
70
--
--
--
10
10
--
--
10
--
--
--
--
--
--
--
--
--
--
70
70
35
--
--
35
30
--
ns
ns
ns
ns
ns
ns
ns
ns
ns
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE1
(1,2,4)
t
RC
ADDRESS
t
D
OUT
t
OH
AA
t
OH
R0201-BS62LV4007
4
Revision 1.1
Jan.
2004
BSI
READ CYCLE2
(1,3,4)
BS62LV4007
CE
t
t
D
OUT
(5)
CLZ
ACS
t
CHZ
(5)
READ CYCLE3
(1,4)
t
RC
ADDRESS
t
OE
AA
t
CE
t
OH
OE
t
t
ACS
t
(5)
CLZ
OLZ
t
OHZ
(5)
(1,5)
t
CHZ
D
OUT
NOTES:
1. WE is high in read Cycle.
2. Device is continuously selected when CE = V
IL
.
3. Address valid prior to or coincident with CE transition low.
4. OE = V
IL
.
5. The parameter is guaranteed but not 100% tested.
R0201-BS62LV4007
5
Revision 1.1
Jan.
2004
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