COTS PEM
COTS
BOOT SECTOR
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016J
16 Megabit (2M x 8-Bit / 1M x 16-Bit)
CMOS 3.0 Volt-Only Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
Single Power Supply Operation
– Full voltage range: 2.7 to 3.6 volt read and write operations for
battery-powered applications
PERFORMANCE CHARACTERISTICS
High Performance
•
•
Access times as fast as 55 ns
Extended temperature range (–40°C to +125°C)
Military temperature range (–55°C to +125°C)
Manufactured on 110 nm Process Technology
•
•
•
•
•
Fully compatible with 200 nm AS29LV016
Ultra Low Power Consumption (typical values at 5 MHz)
Secured Silicon Sector region
128-word/256-byte sector for permanent, secure identification
through an 8-word/16-byte random Electronic Serial Number
accessible through a command sequence
May be programmed and locked at the factory or by the customer
•
•
•
•
0.2 µA Automatic Sleep mode current
0.2 µA standby mode current
7 mA read current
20 mA program/erase current
Cycling Endurance: 1,000,000 cycles per sector typical
Data Retention: 20 years typical
Flexible Sector Architecture
One 16 Kbyte, two 8 Kbyte, one 32 Kbyte, and thirty-one 64
Kbyte sectors (byte mode)
One 8 Kword, two 4 Kword, one 16 Kword, and thirty-one 32
Kword sectors (word mode)
SOFTWARE FEATURES
CFI (Common Flash Interface) Compliant
•
Sector Group Protection Features
Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
•
•
•
A hardware method of locking a sector to prevent any program or
erase operations within that sector
Sectors can be locked in-system or via programming equipment
Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Erase Suspend/Erase Resume
•
Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
Data# Polling and Toggle Bits
Provides a software method of detecting program or erase operation
completion
Unlock Bypass Program Command
•
Reduces overall programming time when issuing multiple program
command sequences
HARDWARE FEATURES
Ready/Busy# Pin (RY/BY#)
Top or Bottom Boot Block Configurations Available
Compatibility with JEDEC standards
•
•
•
•
Pinout and software compatible with single-power supply Flash
Superior inadvertent write protection
Provides a hardware method of detecting program or erase cycle
completion
Hardware Reset Pin (RESET#)
PACKAGE OPTIONS
48-pin TSOP
•
•
Hardware method to reset the device to reading array data
WP# input pin
For boot sector devices: at V
IL
, protects first or last 16 Kbyte
sector depending on boot configuration (top boot or bottom boot)
AS29LV016J
Rev. 0.0 02/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
1
COTS PEM
COTS
BOOT SECTOR
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016J
GENERAL DESCRIPTION
The AS29LV016J is a 16 Mbit, 3.0 Volt-only Flash memory
organized as 2,097,152 bytes or 1,048,576 words. The device
is offered in a 48-pin TSOP package. The word-wide data
(x16) appears on DQ15–DQ0; the byte-wide (x8) data appears
on DQ7–DQ0. This device is designed to be programmed in-
system with the standard system 3.0 volt V
CC
supply. A 12.0 V
V
PP
or 5.0 V
CC
are not required for write or erase operations.
The device can also be programmed in standard EPROM
programmers.
The device offers access time of 55 ns allowing high speed
microprocessors to operate without wait states. To eliminate
bus contention the device has separate chip enable (CE#),
write enable (WE#) and output enable (OE#) controls.
The device requires only a
single 3.0 volt power supply
for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The AS29LV016J is entirely command set compatible with
the
JEDEC single-power-supply Flash standard.
Commands
are written to the command register using standard
microprocessor write timings. Register contents serve as
input to an internal state-machine that controls the erase
and programming circuitry. Write cycles also internally latch
addresses and data needed for the programming and erase
operations. Reading data out of the device is similar to reading
from other Flash or EPROM devices.
Device programming occurs by executing the program
command sequence. This initiates the
Embedded Program
algorithm—an internal algorithm that automatically times the
program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times
by requiring only two write cycles to program data instead of
four.
Device erasure occurs by executing the erase command
sequence. This initiates the
Embedded Erase
algorithm—an
internal algorithm that automatically preprograms the array
(if it is not already programmed) before executing the erase
operation. During erase, the device automatically times the
erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase
operation is complete by observing the RY/BY# pin, or by
reading the DQ7 (Data# Polling) and DQ6 (toggle)
status
bits.
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The
sector erase architecture
allows memory sectors to be
erased and reprogrammed without affecting the data contents
of other sectors. The device is fully erased when shipped
from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during
power transitions. The
hardware sector protection
feature
disables both program and erase operations in any
combination of the sectors of memory. This can be achieved
in-system or via programming equipment.
The
Erase Suspend/Erase Resume
feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any sector that is not selected for erasure.
True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in
progress and resets the internal state machine to reading
array data. The RESET# pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the
automatic sleep mode.
The system
can also place the device into the
standby mode.
Power
consumption is greatly reduced in both these modes.
ASI combines years of flash memory manufacturing
experience to produce the highest levels of quality, reliability
and cost effectiveness. The device electrically erases all bits
within a sector simultaneously via Fowler-Nordheim
tunneling. The data is programmed using hot electron
injection.
AS29LV016J
Rev. 0.0 02/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
2
COTS PEM
COTS
BOOT SECTOR
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016J
PRODUCT SELECTOR GUIDE
Family Part Number
Speed Option
Voltage Range: Vcc = 2.7-3.6V
Vcc =3.0-3.6V
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
AS29LV016J
70
55
55
70
55
70
70
Max OE# access time, nc (t
OE
)
55
Note:
See AC Characteristics on page 29 for full specifications
BLOCK DIAGRAM
RY/BY#
V
CC
V
SS
RESET#
Sector Switches
Erase Voltage
Generator
DQ0–DQ15 (A-1)
Input/Output
Buffers
WE#
BYTE#
WP#
State
Control
Command
Register
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
Data
Latch
CE#
OE#
Y-Decoder
Y-Gating
V
CC
Detector
Timer
Address Latch
X-Decoder
Cell Matrix
A0–A19
AS29LV016J
Rev. 0.0 02/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
3
COTS PEM
COTS
BOOT SECTOR
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016J
PIN CONFIGURATION
A0–A19
=
DQ0–DQ14 =
DQ15/A-1 =
BYTE#
CE#
OE#
WE#
WP#
=
=
=
=
=
20 addresses
15 data inputs/outputs
DQ15 (data input/output, word mode),
A-1 (LSB address input, byte mode)
Selects 8-bit or 16-bit mode
Chip enable
Output enable
Write enable
Write protect: The WP# contains an
internal pull-up; when unconnected,
WP is at V
IH
Hardware reset
Ready/Busy output
3.0 volt-only single power supply (see
Product Selector Guide for speed
options and voltage supply tolerances)
Device ground
Pin not connected internally
LOGIC SYMBOL
20
A0–A19
DQ0–DQ15
(A-1)
CE#
OE#
WE#
RESET#
BYTE#
WP#
RY/BY#
16 or 8
RESET#
RY/BY#
V
CC
V
SS
NC
=
=
=
=
=
CONNECTION DIAGRAMS
A15
A14
A13
A12
A11
A10
A9
A8
A19
NC
WE#
RESET#
NC
WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48 Pin Standard TSOP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
AS29LV016J
Rev. 0.0 02/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
4
COTS PEM
COTS
BOOT SECTOR
BOOT SECTOR FLASH
Austin Semiconductor, Inc.
AS29LV016J
ORDERING INFORMATION
Pb-BASED LEAD FINISH OPTION
AS29LV016JTRG-55/IT
TOP BOOT
AS29LV016JBRG-55/IT
BOTTOM BOOT
AS29LV016JTRG-70/IT
TOP BOOT
AS29LV016JBRG-70/IT
BOTTOM BOOT
AS29LV016JTRG-55/ET TOP BOOT
AS29LV016JBRG-55/ET BOTTOM BOOT
AS29LV016JTRG-70/ET TOP BOOT
AS29LV016JBRG-70/ET BOTTOM BOOT
AS29LV016JTRG-55/XT TOP BOOT
AS29LV016JBRG-55/XT BOTTOM BOOT
AS29LV016JTRG-70/XT TOP BOOT
AS29LV016JBRG-70/XT BOTTOM BOOT
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
Pb-FREE LEAD FINISH OPTION
AS29LV016JTRGR-55/IT TOP BOOT
AS29LV016JBRGR-55/IT BOTTOM BOOT
AS29LV016JTRGR-70/IT TOP BOOT
AS29LV016JBRGR-70/IT BOTTOM BOOT
AS29LV016JTRGR-55/ET TOP BOOT
AS29LV016JBRGR-55/ET BOTTOM BOOT
AS29LV016JTRGR-70/ET TOP BOOT
AS29LV016JBRGR-70/ET BOTTOM BOOT
AS29LV016JTRGR-55/XT TOP BOOT
AS29LV016JBRGR-55/XT BOTTOM BOOT
AS29LV016JTRGR-70/XT TOP BOOT
AS29LV016JBRGR-70/XT BOTTOM BOOT
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
TSOP1-48
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
ENHANCED
TAPE / REEL OPTION (specify on purchase order)
*AVAILABLE PROCESSES
IT = Industrial Temperature Range -40
o
C to +85
o
C
ET = Extended Temperature Range -55
o
C to +125
o
C
XT = Full Military Processing -55
o
C to +125
o
C
AS29LV016J
Rev. 0.0 02/09
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
5
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