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TP0620N3

Description
P-channel enhancement-mode vertical dmos fets
CategoryDiscrete semiconductor    The transistor   
File Size473KB,4 Pages
ManufacturerSupertex
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TP0620N3 Overview

P-channel enhancement-mode vertical dmos fets

TP0620N3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
package instructionCYLINDRICAL, O-PBCY-W3
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresHIGH INPUT IMPEDANCE
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage200 V
Maximum drain current (Abs) (ID)0.4 A
Maximum drain current (ID)0.4 A
Maximum drain-source on-resistance12 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)35 pF
JEDEC-95 codeTO-92
JESD-30 codeO-PBCY-W3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeROUND
Package formCYLINDRICAL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeP-CHANNEL
Maximum power dissipation(Abs)1 W
Certification statusNot Qualified
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formWIRE
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Base Number Matches1
TP0620
Low Threshold
P-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
-200V
R
DS(ON)
(max)
12Ω
I
D(ON)
(min)
-0.75A
V
GS(th)
(max)
-2.4V
Order Number / Package
TO-92
TP0620N3
MIL visual screening available
Features
Low threshold — -2.4 V max
High input impedance
Low input capacitance — 85pF typical
Fast switching speeds
Low on resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex's well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transistors
and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally-induced secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Package Option
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
Note: See Package Outline section for dimensions.
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
SGD
TO-92
11/12/01
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.

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