OX16C950 rev B
High Performance UART
with 128 byte FIFOs
F
EATURES
•
•
•
•
•
•
•
•
•
•
•
•
•
Single full-duplex asynchronous channel
128-byte deep transmitter / receiver FIFO
Fully software compatible with industry standard
16C550 type UARTs
Pin compatible with TL16C550B/C, ST16C650 and
TL16C750
IBM PC/AT compatible
Baud rates up to 15 Mbps in normal mode and
60Mbps in external 1x clock mode
Readable FIFO levels
Flexible clock prescaler from 1 to 31.875
Isochronous mode using external 1x baud rate clock
up to 60Mbps
9-bit data framing as well as 5,6,7 and 8
Detection of bad data in the receiver FIFO
Automated in-band flow control using programmable
Xon/Xoff characters
Transmitter and receiver can be disabled
•
Automated out-of-band flow control using CTS# / RTS#
and DSR# / DTR#
•
Readable in-band and out-of-band flow control status
•
Programmable special character detection
•
Arbitrary trigger levels for receiver and transmitter FIFO
interrupts and automatic in-band and out-of-band flow
control
•
Transmitter idle interrupt (shift register and FIFO both
empty)
•
Optional Infra-red (IrDA) receiver and transmitter
operation
•
RS-485 buffer enable signals
•
Software channel reset
•
Four byte device ID
•
Sleep mode (low operating current)
•
System clock up to 60 MHz (at 5V), 50 MHz at 3.3V
•
44 PLCC and 48 TQFP packages
•
5 volts operation (PLCC), 3.3/ 5V operation TQFP
R
EV
B E
NHANCEMENTS
The OX16C950B is an enhanced, fully backward-compatible revision of the OX16C950 rev A. The chief enhancements are as
follows –
•
All known errata fixed
•
Enhanced features first offered in OX16PCI954 added – these include controls for sleep-mode sensitivity, ability to
read FCR and Good Data Status
•
3V operation possible with 48 pin TQFP
•
Enhanced isochronous clocking options (optional inversions)
•
Enhanced system clock selection options (use of CLKSEL as a clock input)
•
Readable TxRdy, RxRdy status and forcing TxRdy or RxRdy inactive
Hereafter OX16C950 rev B is simply referred to as OX16C950.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141
Oxford Semiconductor 2001
OX16C950 rev B Datasheet R1.2 – May 2001
Part No. OX16C950-PCC60-B
D
ESCRIPTION
The OX16C950 is a single-channel ultra-high performance
UART offering data rates up to 15Mbps and 128-deep
transmitter and receiver FIFOs. Deep FIFOs reduce CPU
overhead and allow utilisation of higher data rates.
It is software compatible with the widely used industry-
standard 16C550 type devices and compatibles, as well as
other OX16C95x family devices. It is pin-compatible with
the TL16C550, ST16C650 devices.
In addition to increased performance and FIFO size, the
OX16C950 also provides enhanced features including
improved flow control. Automated software flow control
using Xon/Xoff and automated hardware flow control using
CTS#/RTS# and DSR#/DTR# prevent FIFO over-run. Flow
control and interrupt thresholds are fully programmable and
readable, enabling programmers to fine-tune the
performance of their system. FIFO levels are readable to
facilitate fast driver applications.
The addition of software reset enables recovery from
unforeseen error condition allowing drivers to restart
gracefully. The OX16C950 supports 9-bit data frames
used in multi-drop industrial protocols. It also offers multiple
external clock options for isochronous applications, e.g.
ISDN, xDSL.
The OX16C950 is ideally suited to PC applications, such
as high-speed COM port add-in cards which enable PC
users to take advantage of the maximum performance of
analogue modems or ISDN terminal adapters. It is also
suitable for any equipment requiring high speed
RS232/RS422/RS485 interfaces. Fabricated in 0.6µm
process, OX16C950 also has a low operating current and
sleep mode for battery powered applications.
Oxford Semiconductor Ltd.
25 Milton Park, Abingdon, Oxon, OX14 4SH, UK
Tel: +44 (0)1235 824900 Fax: +44 (0)1235 821141
Oxford Semiconductor 2001
OX16C950 rev B Datasheet R1.2 – May 2001
Part No. OX16C950-PCC60-B
OXFORD SEMICONDUCTOR LTD.
OX16C950 rev B
C
ONTENTS
FEATURES....................................................................................................................................................................................... 1
REV B ENHANCEMENTS................................................................................................................................................................ 1
DESCRIPTION ................................................................................................................................................................................. 2
CONTENTS ...................................................................................................................................................................................... 3
1 PERFORMANCE COMPARISON .............................................................................................................................................. 5
2 BLOCK DIAGRAM ..................................................................................................................................................................... 6
3 PIN INFORMATION.................................................................................................................................................................... 7
4 PIN DESCRIPTIONS .................................................................................................................................................................. 8
4.1
F
URTHER
P
IN
I
NFORMATION
................................................................................................................................................. 11
5 MODE SELECTION.................................................................................................................................................................. 13
5.1
450 M
ODE
........................................................................................................................................................................... 13
5.2
550 M
ODE
........................................................................................................................................................................... 13
5.3
E
XTENDED
550 M
ODE
.......................................................................................................................................................... 13
5.4
750 M
ODE
........................................................................................................................................................................... 13
5.5
650 M
ODE
........................................................................................................................................................................... 13
5.6
950 M
ODE
........................................................................................................................................................................... 14
6 REGISTER DESCRIPTION TABLES....................................................................................................................................... 15
7 RESET CONFIGURATION....................................................................................................................................................... 19
7.1
H
ARDWARE
R
ESET
............................................................................................................................................................... 19
7.2
S
OFTWARE
R
ESET
............................................................................................................................................................... 19
8 TRANSMITTER & RECEIVER FIFOS...................................................................................................................................... 20
8.1
FIFO C
ONTROL
R
EGISTER
‘FCR’ ......................................................................................................................................... 20
9 LINE CONTROL & STATUS .................................................................................................................................................... 21
9.1
F
ALSE
S
TART
B
IT
D
ETECTION
............................................................................................................................................... 21
9.2
L
INE
C
ONTROL
R
EGISTER
‘LCR’ ........................................................................................................................................... 21
9.3
L
INE
S
TATUS
R
EGISTER
‘LSR’.............................................................................................................................................. 22
10 INTERRUPTS & SLEEP MODE............................................................................................................................................... 23
10.1 I
NTERRUPT
E
NABLE
R
EGISTER
‘IER’ ..................................................................................................................................... 23
10.2 I
NTERRUPT
S
TATUS
R
EGISTER
‘ISR’ ..................................................................................................................................... 24
10.3 I
NTERRUPT
D
ESCRIPTION
..................................................................................................................................................... 24
10.4 S
LEEP
M
ODE
....................................................................................................................................................................... 25
11 MODEM INTERFACE............................................................................................................................................................... 25
11.1 M
ODEM
C
ONTROL
R
EGISTER
‘MCR’ ..................................................................................................................................... 25
11.2 M
ODEM
S
TATUS
R
EGISTER
‘MSR’ ........................................................................................................................................ 26
12 OTHER STANDARD REGISTERS .......................................................................................................................................... 27
12.1 D
IVISOR
L
ATCH
R
EGISTERS
‘DLL & DLM’............................................................................................................................. 27
12.2 S
CRATCH
P
AD
R
EGISTER
‘SPR’ ........................................................................................................................................... 27
13 AUTOMATIC FLOW CONTROL .............................................................................................................................................. 28
13.1 E
NHANCED
F
EATURES
R
EGISTER
‘EFR’................................................................................................................................ 28
13.2 S
PECIAL
C
HARACTER
D
ETECTION
......................................................................................................................................... 29
13.3 A
UTOMATIC
I
N
-
BAND
F
LOW
C
ONTROL
................................................................................................................................... 29
13.4 A
UTOMATIC
O
UT
-
OF
-
BAND
F
LOW
C
ONTROL
........................................................................................................................... 29
14 BAUD RATE GENERATION.................................................................................................................................................... 30
14.1 G
ENERAL
O
PERATION
.......................................................................................................................................................... 30
14.2 C
LOCK
P
RESCALER
R
EGISTER
‘CPR’.................................................................................................................................... 31
14.3 T
IMES
C
LOCK
R
EGISTER
‘TCR’............................................................................................................................................. 31
14.4 I
NPUT
C
LOCK
O
PTIONS
........................................................................................................................................................ 33
14.5 TTL C
LOCK
M
ODULE
........................................................................................................................................................... 33
Data Sheet Revision 1.2
Page 3
OXFORD SEMICONDUCTOR LTD.
OX16C950 rev B
14.6 E
XTERNAL
1
X
C
LOCK
M
ODE
................................................................................................................................................. 33
14.7 C
RYSTAL
O
SCILLATOR
C
IRCUIT
............................................................................................................................................ 33
15 ADDITIONAL FEATURES ....................................................................................................................................................... 34
15.1 A
DDITIONAL
S
TATUS
R
EGISTER
‘ASR’................................................................................................................................... 34
15.2 FIFO F
ILL LEVELS
‘TFL & RFL’............................................................................................................................................ 34
15.3 A
DDITIONAL
C
ONTROL
R
EGISTER
‘ACR’................................................................................................................................ 34
15.4 T
RANSMITTER
T
RIGGER
L
EVEL
‘TTL’..................................................................................................................................... 36
15.5 R
ECEIVER
I
NTERRUPT
. T
RIGGER
L
EVEL
‘RTL’ ....................................................................................................................... 36
15.6 F
LOW
C
ONTROL
L
EVELS
‘FCL & FCH’.................................................................................................................................. 36
15.7 D
EVICE
I
DENTIFICATION
R
EGISTERS
...................................................................................................................................... 36
15.8 C
LOCK
S
ELECT
R
EGISTER
‘CKS’ .......................................................................................................................................... 37
15.9 N
INE
-
BIT
M
ODE
R
EGISTER
‘NMR’ ......................................................................................................................................... 37
15.10
M
ODEM
D
ISABLE
M
ASK
‘MDM’......................................................................................................................................... 38
15.11
R
EADABLE
FCR ‘RFC’ .................................................................................................................................................... 38
15.12
G
OOD
-
DATA STATUS REGISTER
‘GDS’ .............................................................................................................................. 39
15.13
DMA S
TATUS
R
EGISTER
‘DMS’ ....................................................................................................................................... 39
15.14
P
ORT
I
NDEX
R
EGISTER
‘PIX’............................................................................................................................................ 39
15.15
C
LOCK
A
LTERATION
R
EGISTER
‘CKA’............................................................................................................................... 39
16 OPERATING CONDITIONS ..................................................................................................................................................... 40
17 DC ELECTRICAL CHARACTERISTICS.................................................................................................................................. 40
17.1 5V O
PERATION
.................................................................................................................................................................... 40
17.2 3V O
PERATION
.................................................................................................................................................................... 41
18 AC ELECTRICAL CHARACTERISTICS.................................................................................................................................. 42
18.1 5V O
PERATION
.................................................................................................................................................................... 42
18.2 3V O
PERATION
.................................................................................................................................................................... 43
19 TIMING WAVEFORMS............................................................................................................................................................. 44
20 PACKAGE INFORMATION...................................................................................................................................................... 46
21 ORDERING INFORMATION .................................................................................................................................................... 47
NOTES............................................................................................................................................................................................ 48
CONTACT DETAILS ...................................................................................................................................................................... 49
Data Sheet Revision 1.2
Page 4
OXFORD SEMICONDUCTOR LTD.
OX16C950 rev B
1
P
ERFORMANCE
C
OMPARISON
Feature
External 1x baud rate clock
Max baud rate in normal mode
Max baud rate in 1x clock mode
FIFO depth
Sleep mode
Auto Xon/Xoff flow
Auto CTS#/RTS# flow
Auto DSR#/DTR# flow
No. of Rx interrupt thresholds
No. of Tx interrupt thresholds
No. of flow control thresholds
Transmitter empty interrupt
Readable status of flow control
Readable FIFO levels
Clock prescaler options
Rx/Tx disable
Software reset
Device ID
9-bit data frames
RS485 buffer enable
Infra-red (IrDA)
OX16C950
Yes
15 Mbps
60 Mbps
128
Yes
Yes
Yes
Yes
127
128
128
Yes
Yes
Yes
248
Yes
Yes
Yes
Yes
Yes
Yes
16C450
No
115 kbps
n/a
1
No
No
No
No
1
1
n/a
No
n/a
n/a
n/a
No
No
No
No
No
No
16C550
No
115 kbps
n/a
16
No
No
No
No
4
1
n/a
No
No
No
n/a
No
No
No
No
No
No
16C650
No
1.5 Mbps
n/a
32
Yes
Yes
Yes
No
4
4
4
No
No
No
2
No
No
No
No
No
Yes
16C750
No
1 Mbps
n/a
64
Yes
No
Yes
No
4
1
n/a
No
No
No
n/a
No
No
No
No
No
No
Table 1 OX16C950 performance compared with 16C450, 16C550, 16C650 and 16C750 devices
Improvements of the OX16C950 over previous generations of PC UART:
Deeper FIFOs:
OX16C950 offers 128-byte deep FIFOs for the transmitter
and receiver.
Higher data rates:
Transmission and reception baud rates up to 15Mbps. A
flexible clock prescaler offers division ratios of 1 to 31 7/8
in steps of 1/8 using a divide-by-“M N/8” circuitry. The
flexible prescaler allows users to select from a wide variety
of input clock frequencies as well as access to higher baud
rates whilst maintaining compatibility with existing software
drivers (see section 14.2).
External clock options:
The receiver can accept an external 1x clock on the DSR#
input. The transmitter can accept a 1x clock on the RI#
input and/or assert its own (Nx) clock on the DTR# output.
In 1x mode, asynchronous data may be transmitted and
received at speeds up to 60Mbps (see section 14.6).
Automatic flow control:
The UART automatically handles either or both in-band
(software) flow control (transmitting and receiving Xon/Xoff
characters) and out-of-band (hardware) flow control using
the RTS#/CTS# or DSR#/DTR# modem control lines.
Data Sheet Revision 1.2
Special character detection:
The receiver can be programmed to generate an interrupt
upon reception of a particular character value.
Power-down:
The device can be placed in ‘sleep mode’ to conserve
power.
Readable FIFO levels:
Driver efficiency can be improved by using readable FIFO
levels.
Selectable trigger levels:
The receiver FIFO threshold can be arbitrarily
programmed. The transmitter FIFO threshold and
thresholds for automatic flow control can be programmed
to operate at a variety of trigger levels.
Additional control:
The transmitter and receiver can be independently
disabled.
Page 5
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