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TN2524N8

Description
N-channel enhancement-mode vertical dmos fets
CategoryDiscrete semiconductor    The transistor   
File Size474KB,4 Pages
ManufacturerSupertex
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TN2524N8 Overview

N-channel enhancement-mode vertical dmos fets

TN2524N8 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSupertex
Parts packaging codeSOT-89
package instructionSAME AS SOT-89, 3 PIN
Contacts3
Reach Compliance Codeunknown
ECCN codeEAR99
Other featuresLOGIC LEVEL COMPATIBLE
Shell connectionDRAIN
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage240 V
Maximum drain current (ID)0.36 A
Maximum drain-source on-resistance6 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)25 pF
JEDEC-95 codeTO-243AA
JESD-30 codeR-PSSO-F3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power dissipation(Abs)1.6 W
Maximum pulsed drain current (IDM)2 A
Certification statusNot Qualified
surface mountYES
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formFLAT
Terminal locationSINGLE
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
Maximum off time (toff)40 ns
Maximum opening time (tons)20 ns
TN2524
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
240V
*
Same as SOT-89.
R
DS(ON)
(max)
6.0Ω
V
GS(th)
(max)
2.0V
I
D(ON)
(min)
1.0A
Order Number / Package
TO-243AA*
TN2524N8
Die
TN2524ND
Product supplied on 2000 piece carrier tape reels.
† MIL visual screening available.
Product marking for TO-243AA
TN5C❋
Features
Low threshold — 2.0V max.
High input impedance
Low input capacitance — 125pF max.
Fast switching speeds
Low on resistance
Free from secondary breakdown
Low input and output leakage
Complementary N- and P-channel devices
Where
= 2-week alpha date code
Low Threshold DMOS Technology
These low threshold enhancement-mode (normally-off) transis-
tors utilize a vertical DMOS structure and Supertex's well-proven
silicon-gate manufacturing process. This combination produces
devices with the power handling capabilities of bipolar transis-
tors and with the high input impedance and positive temperature
coefficient inherent in MOS devices. Characteristic of all MOS
structures, these devices are free from thermal runaway and
thermally induced secondary breakdown.
Supertex vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where very low threshold
voltage, high breakdown voltage, high input impedance, low input
capacitance, and fast switching speeds are desired.
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Package Option
D
G
D
S
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
11/12/01
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
TO-243AA
(SOT-89)
Note: See Package Outline section for dimensions.
Supertex Inc. does not recommend the use of its products in life support applications and will not knowingly sell its products for use in such applications unless it receives an adequate "products liability
indemnification insurance agreement." Supertex does not assume responsibility for use of devices described and limits its liability to the replacement of devices determined to be defective due to
workmanship. No responsibility is assumed for possible omissions or inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications, refer to the
Supertex website: http://www.supertex.com. For complete liability information on all Supertex products, refer to the most current databook or to the Legal/Disclaimer page on the Supertex website.
1

TN2524N8 Related Products

TN2524N8 TN2524 TN2524ND
Description N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets
Is it Rohs certified? incompatible - incompatible
Parts packaging code SOT-89 - DIE
package instruction SAME AS SOT-89, 3 PIN - UNCASED CHIP, X-XUUC-N
Reach Compliance Code unknown - compliant
ECCN code EAR99 - EAR99
Other features LOGIC LEVEL COMPATIBLE - LOGIC LEVEL COMPATIBLE, HIGH INPUT IMPEDANCE, LOW THRESHOLD
Configuration SINGLE WITH BUILT-IN DIODE - SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 240 V - 240 V
Maximum drain-source on-resistance 6 Ω - 6 Ω
FET technology METAL-OXIDE SEMICONDUCTOR - METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss) 25 pF - 25 pF
JESD-30 code R-PSSO-F3 - X-XUUC-N
JESD-609 code e0 - e0
Number of components 1 - 1
Number of terminals 3 - 3
Operating mode ENHANCEMENT MODE - ENHANCEMENT MODE
Maximum operating temperature 150 °C - 150 °C
Package body material PLASTIC/EPOXY - UNSPECIFIED
Package shape RECTANGULAR - UNSPECIFIED
Package form SMALL OUTLINE - UNCASED CHIP
Peak Reflow Temperature (Celsius) NOT SPECIFIED - NOT SPECIFIED
Polarity/channel type N-CHANNEL - N-CHANNEL
Certification status Not Qualified - Not Qualified
surface mount YES - YES
Terminal surface Tin/Lead (Sn/Pb) - TIN LEAD
Terminal form FLAT - NO LEAD
Terminal location SINGLE - UPPER
Maximum time at peak reflow temperature NOT SPECIFIED - NOT SPECIFIED
transistor applications SWITCHING - SWITCHING
Transistor component materials SILICON - SILICON
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