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TN2106N3

Description
N-channel enhancement-mode vertical dmos fets
CategoryDiscrete semiconductor    The transistor   
File Size26KB,4 Pages
ManufacturerSupertex
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TN2106N3 Overview

N-channel enhancement-mode vertical dmos fets

TN2106N3 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSupertex
Parts packaging codeTO-92
package instructionCYLINDRICAL, O-PBCY-T3
Contacts3
Reach Compliance Codecompliant
ECCN codeEAR99
Other featuresLOW THRESHOLD, LOGIC LEVEL COMPATIBLE
ConfigurationSINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage60 V
Maximum drain current (ID)0.3 A
Maximum drain-source on-resistance2.5 Ω
FET technologyMETAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss)8 pF
JEDEC-95 codeTO-92
JESD-30 codeO-PBCY-T3
JESD-609 codee0
Number of components1
Number of terminals3
Operating modeENHANCEMENT MODE
Maximum operating temperature150 °C
Package body materialPLASTIC/EPOXY
Package shapeROUND
Package formCYLINDRICAL
Peak Reflow Temperature (Celsius)NOT SPECIFIED
Polarity/channel typeN-CHANNEL
Maximum power consumption environment1 W
Maximum power dissipation(Abs)1 W
Certification statusNot Qualified
surface mountNO
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formTHROUGH-HOLE
Terminal locationBOTTOM
Maximum time at peak reflow temperatureNOT SPECIFIED
transistor applicationsSWITCHING
Transistor component materialsSILICON
TN2106
Low Threshold
N-Channel Enhancement-Mode
Vertical DMOS FETs
Ordering Information
BV
DSS
/
BV
DGS
60V
R
DS(ON)
(max)
2.5Ω
V
GS(th)
(max)
2.0V
Order Number / Package
TO-236AB*
TN2106K1
TO-92
TN2106N3
Die
TN2106ND
Product marking for SOT-23:
N1Lp
where
p
= 2-week alpha date code
*Same as SOT-23. All units shipped on 3,000 piece carrier tape reels.
Features
Free from secondary breakdown
Low power drive requirement
Ease of paralleling
Low C
ISS
and fast switching speeds
Excellent thermal stability
Integral Source-Drain diode
High input impedance and high gain
Complementary N- and P-channel devices
Advanced DMOS Technology
These enhancement-mode (normally-off) transistors utilize a
vertical DMOS structure and Supertex’s well-proven silicon-gate
manufacturing process. This combination produces devices with
the power handling capabilities of bipolar transistors and with the
high input impedance and positive temperature coefficient inher-
ent in MOS devices. Characteristic of all MOS structures, these
devices are free from thermal runaway and thermally-induced
secondary breakdown.
Supertex’s vertical DMOS FETs are ideally suited to a wide range
of switching and amplifying applications where high breakdown
voltage, high input impedance, low input capacitance, and fast
switching speeds are desired.
Applications
Logic level interfaces – ideal for TTL and CMOS
Solid state relays
Battery operated systems
Photo voltaic drives
Analog switches
General purpose line drivers
Telecom switches
Drain
Package Options
Absolute Maximum Ratings
Drain-to-Source Voltage
Drain-to-Gate Voltage
Gate-to-Source Voltage
Operating and Storage Temperature
Soldering Temperature*
*
Distance of 1.6 mm from case for 10 seconds.
Note: See Package Outline section for dimensions.
BV
DSS
BV
DGS
±
20V
-55°C to +150°C
300°C
Gate
Source
S G D
TO-236AB
(SOT-23)
top view
TO-92
7-71

TN2106N3 Related Products

TN2106N3 TN2106K1
Description N-channel enhancement-mode vertical dmos fets N-channel enhancement-mode vertical dmos fets
Is it Rohs certified? incompatible incompatible
Maker Supertex Supertex
Parts packaging code TO-92 SOT-23
package instruction CYLINDRICAL, O-PBCY-T3 SMALL OUTLINE, R-PDSO-G3
Contacts 3 3
Reach Compliance Code compliant compliant
ECCN code EAR99 EAR99
Other features LOW THRESHOLD, LOGIC LEVEL COMPATIBLE LOW THRESHOLD, LOGIC LEVEL COMPATIBLE
Configuration SINGLE WITH BUILT-IN DIODE SINGLE WITH BUILT-IN DIODE
Minimum drain-source breakdown voltage 60 V 60 V
Maximum drain current (ID) 0.3 A 0.28 A
Maximum drain-source on-resistance 2.5 Ω 2.5 Ω
FET technology METAL-OXIDE SEMICONDUCTOR METAL-OXIDE SEMICONDUCTOR
Maximum feedback capacitance (Crss) 8 pF 8 pF
JEDEC-95 code TO-92 TO-236AB
JESD-30 code O-PBCY-T3 R-PDSO-G3
JESD-609 code e0 e0
Number of components 1 1
Number of terminals 3 3
Operating mode ENHANCEMENT MODE ENHANCEMENT MODE
Maximum operating temperature 150 °C 150 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
Package shape ROUND RECTANGULAR
Package form CYLINDRICAL SMALL OUTLINE
Peak Reflow Temperature (Celsius) NOT SPECIFIED NOT SPECIFIED
Polarity/channel type N-CHANNEL N-CHANNEL
Maximum power dissipation(Abs) 1 W 0.36 W
Certification status Not Qualified Not Qualified
surface mount NO YES
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form THROUGH-HOLE GULL WING
Terminal location BOTTOM DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED
transistor applications SWITCHING SWITCHING
Transistor component materials SILICON SILICON

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