Enpirion
®
Power Datasheet
EP5352QI/EP5362QI/EP5382QI
500/600/800mA PowerSoC
Synchronous Buck Regulators
With Integrated Inductor
V
IN
Product Overview
The Ultra-Low-Profile EP53X2QI product family
is targeted to applications where board area and
profile are critical. EP53X2QI is a complete
power conversion solution requiring only two low
cost ceramic MLCC caps. Inductor, MOSFETS,
PWM, and compensation are integrated into a
tiny 5mm x 4mm x 1.1mm QFN package. The
EP53x2QI family is engineered to simplify design
and to minimize layout constraints.
High
switching frequency and internal type III
compensation
provides
superior
transient
response. With a 1.1 mm profile, the EP53x2 is
perfect for space and height limited applications.
A 3-pin VID output voltage select scheme
provides seven pre-programmed output voltages
along with an option for external resistor divider.
Output voltage can be programmed on-the-fly to
provide fast, dynamic voltage scaling.
UVLO
Thermal Limit
Current Limit
ENABLE
Soft Start
P-Drive
(-)
PWM
Comp
(+)
Logic
N-Drive
V
OUT
GND
Sawtooth
Generator
Compensation
Network
V
SENSE
(-)
Error
Amp
(+)
Switch
V
FB
DAC
VREF
Voltage
Select
Package Boundry
VS0 VS1 VS2
Product Highlights
•
Revolutionary integrated inductor
•
Very small solution foot print*
•
Fully RoHS compliant; MSL 3 260°C reflow
•
Only two low cost components required
•
5mm x 4mm x1.1mm QFN package
•
Wide 2.4V to 5.5V input range
•
500, 600, 800 mA output current versions
•
Less than 1
µA
standby current
•
4 MHz switching frequency
•
Fast transient response
•
Very low ripple voltage; 5mV
p-p
typical
•
3 Pin VID Output Voltage select
•
External divider option
•
Dynamically adjustable output
•
Designed for Low noise/EMI
•
Short circuit, UVLO, and thermal protection
Typical Application Circuit
ENABLE
V
Sense
V
out
10µF
V
IN
2.2uF
V
OUT
V
in
Voltage
Select
V
S0
V
S1
V
S2
V
FB
GND
Figure 1. Typical application circuit.
Applications
•
•
•
•
•
•
Area constrained applications
Mobile multimedia, smartphone & PDA
Mobile and Cellular platforms
VoIP and Video phones
Personal Media Players
FPGA, DSP, IO & Peripherals
1
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October 11, 2013
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Rev H
EP5382QI/EP5362QI/EP5352QI
Absolute Maximum Ratings
CAUTION: Absolute Maximum ratings are stress ratings only. Functional operation beyond recommended operating
conditions is not implied. Stress beyond absolute maximum ratings may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended periods may affect device reliability.
PARAMETER
Input Supply Voltage
Voltages on: ENABLE, V
SENSE
, V
S0
-V
S2
Voltage on: V
FB
Storage Temperature Range
Reflow Temp, 10 Sec, MSL3 JEDEC J-STD-020A
ESD Rating (based on Human Body Model)
SYMBOL
V
IN
MIN
-0.3
-0.3
-0.3
-65
MAX
7.0
V
IN
+ 0.3
2.7
150
260
2000
UNITS
V
V
V
°C
°C
V
T
STG
Recommended Operating Conditions
PARAMETER
Input Voltage Range
Output Voltage Range
Operating Ambient Temperature
Operating Junction Temperature
SYMBOL
V
IN
V
OUT
T
A
T
J
MIN
2.4
0.6
-40
-40
MAX
5.5
V
IN
-0.45
+85
+125
UNITS
V
V
°C
°C
Thermal Characteristics
PARAMETER
Thermal Resistance: Junction to Ambient (0 LFM)
Thermal Resistance: Junction to Case (0 LFM)
Thermal Shutdown
Thermal Shutdown Hysteresis
SYMBOL
θ
JA
θ
JC
T
J-TP
TYP
65
15
+150
15
UNITS
°C/W
°C/W
°C
°C
Electrical Characteristics
NOTE: T
A
= 25°C unless otherwise noted. Typical values are at VIN = 3.6V.
EP5352QI, EP5362QI: C
IN
= 2.2µF, C
OUT
=10uF.
EP5382QI: C
IN
= 4.7µF, C
OUT
=10uF.
PARAMETER
Operating Input Voltage
Under Voltage Lockout
UVLO Hysteresis
V
OUT
Initial Accuracy
V
OUT
Variation for all
Causes
SYMBOL
V
IN
V
UVLO
V
OUT
V
OUT
TEST CONDITIONS
VIN going low to high
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 100mA;
T
A
= 25C
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 0 –
800mA,
T
A
= -40°C to +85°C
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 100mA
VSO=VS1=VS2=1
2.4V ≤ V
IN
≤ 5.5V, I
LOAD
= 0-800mA,
-2.0
-3.0
MIN
2.4
TYP
2.2
0.145
MAX
5.5
2.3
+2.0
+3.0
UNITS
V
V
V
%
%
Feedback Pin Voltage
Feedback Pin Input Current
Feedback Pin Voltage
V
FB
I
FB
V
FB
0.591
0.585
0.603
1
0.603
0.615
0.621
V
nA
V
2
03132
October 11, 2013
www.altera.com/enpirion
Rev H
EP5382QI/EP5362QI/EP5352QI
PARAMETER
SYMBOL
TEST CONDITIONS
T
A
= -40°C to +85°C
VSO=VS1=VS2=1
EP5352QI
EP5362QI
EP5382QI
Enable = Low
No switching
2.4V
≤
V
IN
≤
5.5V,
0.6V
≤
V
OUT
≤
V
IN
– 0.6V
Pin = Low
Pin = High
Logic Low
Logic High
V
IN
= 3.6V
MIN
TYP
MAX
UNITS
Dynamic Voltage Slew Rate
Continuous Output Current
EP5352QI
Continuous Output Current
EP5362QI
Continuous Output Current
EP5382QI
Shut-Down Current
Quiescent Current
PFET OCP Threshold
VS0-VS1 Voltage
Threshold
VS0-VS2 Pin Input Current
Enable Voltage Threshold
Enable Pin Input Current
Operating Frequency
PFET On Resistance
NFET On Resistance
Internal Inductor DCR
Soft-Start Operation
Soft-Start Slew Rate
VOUT Rise Time
V
slew
I
OUT
I
OUT
I
OUT
I
SD
I
LIM
500
600
800
3
V/mS
mA
mA
mA
0.75
800
1.4
0.0
1.4
1
0.0
1.4
2
4
340
270
.110
1.95
1.56
3
2.4
4.05
3.24
0.2
V
IN
2
0.4
V
IN
µA
µA
A
V
nA
V
µA
MHz
mΩ
mΩ
Ω
V/mS
mS
I
VSX
I
EN
F
OSC
R
DS(ON)
R
DS(ON)
VSS
TSS
VID programming mode
VFB programming mode
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03132
October 11, 2013
www.altera.com/enpirion
Rev H
EP5382QI/EP5362QI/EP5352QI
Pin Description
ENABLE
ENABLE
20
VS1
VS0
VS2
VS1
18
18
20
19
17
VS2
V
IN
V
IN
GND
GND
V
OUT
V
OUT
1
2
3
4
5
6
16
15
14
13
12
11
V
FB
V
SENSE
NC
NC
NC
NC
V
FB
V
SENSE
NC
NC
NC
NC
17
19
VS0
16
15
14
13
12
11
Thermal
Pad
1
2
3
4
5
6
V
IN
V
IN
GND
GND
V
OUT
V
OUT
10
10
Figure 2. Pin description, top view.
V
IN
(Pin 1,2): Input voltage pin. Supplies power
to the IC. V
IN
can range from 2.4V to 5.5V.
Input GND:
(Pin 3): Input power ground.
Connect this pin to the ground terminal of the
input capacitor.
Refer to
Layout
Recommendations for further details.
Output GND:
(Pin 4): Power ground. The
output filter capacitor should be connected to
this pin. Refer to Layout recommendations for
further detail.
V
OUT
(Pin 5,6,7): Regulated output voltage.
NC
(Pin 8,9,10,11,12,13,14): These pins
should not be electrically connected to each
other or to any external signal, voltage, or
ground. One or more of these pins may be
connected internally.
V
SENSE
(Pin 15): Sense pin for output voltage
regulation.
Connect V
SENSE
to the output
voltage rail as close to the terminal of the
output filter capacitor as possible.
7
8
9
9
8
7
V
OUT
NC
NC
NC
NC
NC
NC
Figure 3. Pin description, bottom view.
V
FB
(Pin 16): Feed back pin for external divider
option. When using the external divider option
(VS0=VS1=VS2= high) connect this pin to the
center of the external divider. Set the divider
such that V
FB
= 0.603V.
VS0,VS1,VS2
(Pin 17,18,19): Output voltage
select. VS0=pin19, VS1=pin18, VS2=pin17.
Selects one of seven preset output voltages or
choose external divider by connecting pins to
logic high or low. Logic low is defined as V
LOW
≤
0.4V. Logic high is defined as V
HIGH
≥
1.4V.
Any level between these two values is
indeterminate. (refer to section on output
voltage select for more detail).
ENABLE
(Pin 20): Output enable. Enable =
logic high, disable = logic low. Logic low is
defined as V
LOW
≤
0.2V. Logic high is defined
as V
HIGH
≥
1.4V. Any level between these two
values is indeterminate.
Thermal Pad.
Thermal pad to remove heat
from package. Connect to surface ground pad
and PCB internal ground plane.
V
OUT
4
03132
October 11, 2013
www.altera.com/enpirion
Rev H
EP5382QI/EP5362QI/EP5352QI
Functional Block Diagram
V
IN
UVLO
Thermal Limit
Current Limit
ENABLE
Soft Start
P-Drive
(-)
PWM
Comp
(+)
Logic
N-Drive
V
OUT
GND
Sawtooth
Generator
Compensation
Network
V
SENSE
(-)
Error
Amp
(+)
Switch
V
FB
DAC
VREF
Voltage
Select
Package Boundry
VS0 VS1 VS2
Figure 4. Functional block diagram.
5
03132
October 11, 2013
www.altera.com/enpirion
Rev H
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