TS68040VR33A datasheet, PDF - EEWORLD Datasheet

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TS68040VR33A: Description32-BIT, 25 MHz, MICROPROCESSOR, CQFP196; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，49 Pages; ManufacturerAtmel (Microchip)

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TS68040VR33A Overview

32-BIT, 25 MHz, MICROPROCESSOR, CQFP196

TS68040VR33A Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Parts packaging code	PGA
package instruction	PGA, PGA179,18X18
Contacts	179
Reach Compliance Code	unknow
ECCN code	3A991.A.2
Address bus width	32
bit size	32
boundary scan	YES
maximum clock frequency	33 MHz
External data bus width	32
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CPGA-P179
length	47.244 mm
low power mode	NO
Number of terminals	179
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	PGA
Encapsulate equivalent code	PGA179,18X18
Package shape	SQUARE
Package form	GRID ARRAY
power supply	5 V
Certification status	Not Qualified
Maximum seat height	3.275 mm
speed	33 MHz
Maximum supply voltage	5.25 V
Minimum supply voltage	4.75 V
Nominal supply voltage	5 V
surface mount	NO
technology	HCMOS
Terminal form	PIN/PEG
Terminal pitch	2.54 mm
Terminal location	PERPENDICULAR
width	47.244 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR
Base Number Matches	1

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Features

•

26-42 MIPS Integer Performance

3.5-5.6 MFLOPS Floating-Point-Performance

IEEE 754-Compatible FPU

Independent Instruction and Data MMUs

4K bytes Physical Instruction Cache and 4K bytes Physical Data Cache Accessed

Simultaneously

32-bit, Nonmultiplexed External Address and Data Buses with Synchronous Interface

User-Object-Code Compatibility with All Earlier TS68000 Microprocessors

Multimaster/Multiprocessor Support via Bus Snooping

Concurrent Integer Unit, FPU, MMU, Bus Controller, and Bus Snooper Maximize

Throughput

4G bytes Direct Addressing Range

Software Support Including Optimizing C Compiler and UNIX

System V Port

IEEE P 1149-1 Test Mode (JTAG)

f = 25 MHz, 33 MHz; V

= 5V ± 5%; P

= 7W

The Use of the TS88915T Clock Driver is Suggested

Third-

Generation

32-bit

Microprocessor

TS68040

Description

The TS68040 is Atmel’s third generation of 68000-compatible, high-performance, 32-

bit microprocessors. The TS68040 is a virtual memory microprocessor employing

multiple, concurrent execution units and a highly integrated architecture to provide

very high performance in a monolithic HCMOS device. On a single chip, the TS68040

integrates a 68030-compatible integer unit, an IEEE 754-compatible floating-point unit

(FPU), and fully independent instruction and data demand-paged memory manage-

ment units (MMUs), including 4K bytes independent instruction and data caches. A

high degree of instruction execution parallelism is achieved through the use of multi-

ple independent execution pipelines, multiple internal buses, and a full internal

Harvard architecture, including separate physical caches for both instruction and data

accesses. The TS68040 also directly supports cache coherency in multimaster appli-

cations with dedicated on-chip bus snooping logic.

The TS68040 is user-object-code compatible with previous members of the TS68000

Family and is specifically optimized to reduce the execution time of compiler-gener-

ated code. The 68040 HCMOS technology, provides an ideal balance between speed,

power, and physical device size.

Figure 1 is a simplified block diagram of the TS68040. Instruction execution is pipe-

lined in both the integer unit and FPU. Independent data and instruction MMUs control

the main caches and the address translation caches (ATCs). The ATCs speed up log-

ical-to-physical address translations by storing recently used translations. The bus

snooper circuit ensures cache coherency in multimaster and multiprocessing

applications.

Screening

•

MIL-STD-883

DESC. Drawing 5962-93143

Atmel Standards

Rev. 2116A–HIREL–09/02

TS68040

Introduction

The TS68040 is an enhanced, 32-bit, HCMOS microprocessor that combines the inte-

ger unit processing capabilities of the TS68030 microprocessor with independent

4K bytes data and instruction caches and an on-chip FPU. The TS68040 maintains the

32-bit registers available with the entire TS68000 Family as well as the 32-bit address

and data paths, rich instruction set, and versatile addressing modes. Instruction execu-

tion proceeds in parallel with accesses to the internal caches, MMU operations, and bus

controller activity. Additionally, the integer unit is optimized for high-level language

environments.

The TS68040 FPU is user-object-code compatible with the TS68882 floating-point

coprocessor and conforms to the ANSI/IEEE Standard 754 for binary floating-point arith-

metic. The FPU has been optimized to execute the most commonly used subset of the

TS68882 instruction set, and includes additional instruction formats for single and dou-

ble-precision rounding of results. Floating-point instructions in the FPU execute

concurrently with integer instructions in the integer unit.

The MMUs support multiprocessing, virtual memory systems by translating logical

addresses to physical addresses using translation tables stored in memory. The MMUs

store recently used address mappings in two separate ATCs-on-chip. When an ATC

contains the physical address for a bus cycle requested by the processor, a translation

table search is avoided and the physical address is supplied immediately, incurring no

delay for address translation. Each MMU has two transparent translation registers avail-

able that define a one-to-one mapping for address space segments ranging in size from

16M bytes to 4G bytes each.

Each MMU provides read-only and supervisor-only protections on a page basis. Also,

processes can be given isolated address spaces by assigning each a unique table

structure and updating the root pointer upon a task swap. Isolated address spaces pro-

tect the integrity of independent processes.

The instruction and data caches operate independently from the rest of the machine,

storing information for fast access by the execution units. Each cache resides on its own

internal address bus and internal data bus, allowing simultaneous access to both. The

data cache provides write through or copyback write modes that can be configured on a

page-by-page basis.

The TS68040 bus controller supports a high-speed, non multiplexed, synchronous

external bus interface, which allows the following transfer sizes: byte, word (2 bytes),

long word (4 bytes), and line (16 bytes). Line accesses are performed using burst trans-

fers for both reads and writes to provide high data transfer rates.

2116A–HIREL–09/02

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