VSC8114QB1 datasheet, PDF - EEWORLD Datasheet

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VSC8114QB1: Descriptionatm/sonet/sdh 622 Mb/s transceiver mux/Demux with integrated clock generation and clock recovery; CategoryWireless rf/communication Telecom circuit; File Size435KB，24 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC8114QB1 Overview

atm/sonet/sdh 622 Mb/s transceiver mux/Demux with integrated clock generation and clock recovery

VSC8114QB1 Parametric

Parameter Name	Attribute value
Maker	Vitesse Semiconductor Corporation
Parts packaging code	QFP
package instruction	HQFP, QFP100,.7X.9
Contacts	100
Reach Compliance Code	unknown
app	ATM;SDH;SONET
JESD-30 code	R-PQFP-G100
length	20 mm
Number of functions	1
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	HQFP
Encapsulate equivalent code	QFP100,.7X.9
Package shape	RECTANGULAR
Package form	FLATPACK, HEAT SINK/SLUG
power supply	3.3,3.3/5 V
Certification status	Not Qualified
Maximum seat height	3.4 mm
Nominal supply voltage	3.3 V
surface mount	YES
technology	GAAS
Telecom integrated circuit types	ATM/SONET/SDH MUX/DEMUX
Temperature level	OTHER
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8114

Features

•

Operates at STS-12/STM-4 (622.08Mb/s)

Data Rate

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

• Loss of Signal (LOS) Input & LOS Detection

• +3.3V/5V Programmable PECL Serial Interface

• Provides Equipment, Facilities and Split Loop-

back Modes as well as Loop Timing Mode

• Provide PECL Reference Clock Inputs

• Meets Bellcore, ITU and ANSI Specifications

for Jitter Performance

• Low Power - 0.9Watts Typical

• 100 PQFP Package

• Compatible with Industry ATM UNI Devices

• On Chip Clock Generation of the 622.08MHz

High Speed Clock (Mux)

• On Chip Clock Recovery of the 622.08MHz

High Speed Clock (Demux)

• 8-Bit Parallel TTL Interface with Parity Error

Detection and Generation

• SONET/SDH Frame Recovery

General Description

The VSC8114 is an ATM/SONET/SDH compatible transceiver integrating an on-chip Clock Multiplication

Unit (PLL) for high speed clock generation as well as a Clock and data Recovery Unit (CRU) with 8-bit serial-

to-parallel and parallel-to-serial data conversion. The PLL clock is used for serialization in the transmit direc-

tion (Mux). The recovered clock is used for deserialization in the receive direction (Demux). The demultiplexer

contains SONET/SDH frame detection and recovery. In addition, the device provides both facility and equip-

ment loopback modes and a loop time mode. The part is packaged in a 100PQFP with an integrated heat

spreader for optimum thermal performance and reduced cost. The VSC8114 provides an integrated solution for

ATM physical layers and SONET/SDH systems applications.

Functional Description

The VSC8114 is designed to provide a SONET/SDH compliant interface between the high speed optical

networks and the lower speed User Network Interface devices such as the PM5355 S/UNI-622. The VSC8114

converts 8 bit parallel data at 77.76Mb/s to a serial bit stream at 622.08Mb/s. The device also provides a Facility

Loopback function which loops the received high speed data and clock (optionally recovered on-chip) directly

to the high speed transmit outputs. A Clock Multiplier Unit (CMU) is integrated into the transmit circuit to gen-

erate the high speed clock for the serial output data stream from input reference frequencies of 19.44 or 77.76

MHz. The CMU can be bypassed with the received/recovered clock in loop timing mode, thus synchronizing

the entire part to a single clock. The block diagram on page 2 shows the major functional blocks associated with

the VSC8114.

The receive section provides the serial-to-parallel conversion, converting 622Mb/s bit stream to an 8 bit par-

allel output at 77.76MHz. A Clock Recovery Unit (CRU) is integrated into the receive circuit to recover the high

speed clock from the received serial data stream. The receive section provides an Equipment Loopback function

which will loop the low speed transmit data and clock back through the receive section to the 8 bit parallel out-

puts. The VSC8114 also provides the option of selecting between either its internal CRU’s clock and data sig-

nals, or optics containing a CRU clock and data signals. The receive section also contains a SONET/SDH frame

G52185-0, Rev 4.0

11/1/99

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC8114

ATM/SONET/SDH 622 Mb/s Transceiver Mux/Demux

with Integrated Clock Generation and Clock Recovery

sion of the input reference clock. External control input REFSEL selects the multiply ratio of the CMU (see

table 11). A divide-by-8 version of the CMU clock (TXLSCKOUT) should be used to synchronize the transmit

interface of the UNI device to the transmit input registers on the VSC8114 (see Application Notes, p. 20).

Figure 1: Data and Clock Transmit Block Diagram

VSC8114

PM5355

TXDATAOUT+

TXDATAOUT-

Q D

TXIN[7:0]

Q D

TXLSCKIN

REFCLK

CMU

Divide-by-8

TXLSCKOUT

Receive Section

High speed Non-Return to Zero (NRZ) serial data at 622Mb/s are received by the RXDATAIN inputs. The

CRU recovers the high speed clock from the serial data input. The serial data is converted to byte-wide parallel

data and presented on RXOUT[7:0] pins. A divide-by-8 version of the high-speed clock (RXLSCKOUT)

should be used to synchronize the byte-serial RXOUT[7:0] data with the receive portion of the UNI device. The

on-chip CRU is by-passed by setting the DSBLCRU input high. In this mode, the serial input data and corre-

sponding clock are received by the RXDATAIN and RXCLKIN inputs respectively. RXDATAIN is clocked in

on the rising edge of RXCLKIN+. See Figure 2.

The receive section also includes frame detection and recovery circuitry which detects the SONET/SDH

frame, aligns the received serial data on byte boundaries, and initiates a frame pulse on FP coincident with the

byte aligned data. The frame recovery is initiated when OOF is held high which must occur at least 4 byte clock

cycles before the A1A2 boundary. The OOF input control is a level-sensitive signal, and the VSC8114 will con-

tinually perform frame detection and recovery as long as this pin is held high even if 1 or more frames has been

detected. Frame detection and recovery occurs when a series of three A1 bytes followed by three A2 bytes has

been detected. The parallel output data on RXOUT[7:0] will be byte aligned starting on the third A2 byte. When

a frame is detected, a single byte clock period long pulse is generated on FP which is synchronized with the

byte-aligned third A2 byte on RXOUT[7:0]. The frame detector sends an FP pulse only if OOF is high.

Loss of Signal

The VSC8114 features Loss of Signal (LOS) detection. Loss of Signal is detected if the incoming serial

data stream has no transition continuously for more than 128 bits. During an LOS condition, the VSC8114

forces the receive data low which is an indication for any downstream equipment that an optical interface failure

has occurred. The receive section continues to be clocked by the CRU as it is now locked to the CRUREFCLK

unless DSBLCRU is active, in which case it will be clocked by the CMU. This LOS condition will be removed

when the part detects more than 16 transitions in a 128 bit time window. This LOS detection feature can be dis-

abled by applying a high level to the LOSDETEN_ input. The VSC8114 also has a TTL input LOSTTL and a

G52185-0, Rev 4.0

11/1/99

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 3

VSC8114QB1 Related Products

	VSC8114QB1	VSC8114QB	VSC8114	VSC8114QB2
Description	atm/sonet/sdh 622 Mb/s transceiver mux/Demux with integrated clock generation and clock recovery	atm/sonet/sdh 622 Mb/s transceiver mux/Demux with integrated clock generation and clock recovery	atm/sonet/sdh 622 Mb/s transceiver mux/Demux with integrated clock generation and clock recovery	atm/sonet/sdh 622 Mb/s transceiver mux/Demux with integrated clock generation and clock recovery
Maker	Vitesse Semiconductor Corporation	Vitesse Semiconductor Corporation	-	Vitesse Semiconductor Corporation
Parts packaging code	QFP	QFP	-	QFP
package instruction	HQFP, QFP100,.7X.9	HQFP, QFP100,.7X.9	-	HQFP, QFP100,.7X.9
Contacts	100	100	-	100
Reach Compliance Code	unknown	unknown	-	unknown
app	ATM;SDH;SONET	ATM;SDH;SONET	-	ATM;SDH;SONET
JESD-30 code	R-PQFP-G100	R-PQFP-G100	-	R-PQFP-G100
length	20 mm	20 mm	-	20 mm
Number of functions	1	1	-	1
Number of terminals	100	100	-	100
Maximum operating temperature	85 °C	70 °C	-	85 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-	PLASTIC/EPOXY
encapsulated code	HQFP	HQFP	-	HQFP
Encapsulate equivalent code	QFP100,.7X.9	QFP100,.7X.9	-	QFP100,.7X.9
Package shape	RECTANGULAR	RECTANGULAR	-	RECTANGULAR
Package form	FLATPACK, HEAT SINK/SLUG	FLATPACK, HEAT SINK/SLUG	-	FLATPACK, HEAT SINK/SLUG
power supply	3.3,3.3/5 V	3.3,3.3/5 V	-	3.3,3.3/5 V
Certification status	Not Qualified	Not Qualified	-	Not Qualified
Maximum seat height	3.4 mm	3.4 mm	-	3.4 mm
Nominal supply voltage	3.3 V	3.3 V	-	3.3 V
surface mount	YES	YES	-	YES
technology	GAAS	GAAS	-	GAAS
Telecom integrated circuit types	ATM/SONET/SDH MUX/DEMUX	ATM/SONET/SDH MUX/DEMUX	-	ATM/SONET/SDH MUX/DEMUX
Temperature level	OTHER	COMMERCIAL	-	INDUSTRIAL
Terminal form	GULL WING	GULL WING	-	GULL WING
Terminal pitch	0.65 mm	0.65 mm	-	0.65 mm
Terminal location	QUAD	QUAD	-	QUAD
width	14 mm	14 mm	-	14 mm

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