ICX259AK
Diagonal 6mm (Type 1/3) CCD Image Sensor for PAL Color Video Cameras
Description
The ICX259AK is an interline CCD solid-state
image sensor suitable for PAL color video cameras
with a diagonal 6mm (Type 1/3) system. Compared
with the current product ICX059CK, basic
characteristics such as sensitivity, smear, dynamic
range and S/N are improved drastically through the
adoption of EXview HAD CCD
TM
technology.
This chip features a field period readout system and
an electronic shutter with variable charge-storage
time.
EXview HAD CCD
TM
has different spectral characteristics
from the current CCD.
Features
•
High sensitivity (+7dB compared with the ICX059CK)
•
Low smear (–20dB compared with the ICX059CK)
•
High D range (+5dB compared with the ICX059CK)
•
High S/N
•
High resolution and low dark current
•
Excellent antiblooming characteristics
•
Ye, Cy, Mg, and G complementary color mosaic filters on chip
•
Continuous variable-speed shutter
•
No voltage adjustment
(Reset gate and substrate bias are not adjusted.)
•
Reset gate:
5V drive
•
Horizontal register: 5V drive
16 pin DIP (Plastic)
Pin 1
2
V
12
3
Pin 9
H
40
Optical black position
(Top View)
Device Structure
•
Interline CCD image sensor
•
Image size:
Diagonal 6mm (Type 1/3)
•
Number of effective pixels: 752 (H)
×
582 (V) approx. 440K pixels
•
Total number of pixels:
795 (H)
×
596 (V) approx. 470K pixels
•
Chip size:
6.00mm (H)
×
4.96mm (V)
•
Unit cell size:
6.50µm (H)
×
6.25µm (V)
•
Optical black:
Horizontal (H) direction : Front 3 pixels, rear 40 pixels
Vertical (V) direction
: Front 12 pixels, rear 2 pixels
•
Number of dummy bits:
Horizontal 22
Vertical 1 (even fields only)
•
Substrate material:
Silicon
TM
∗
EXview HAD CCD is a trademark of Sony Corporation.
EXview HAD CCD is a CCD that drastically improves light efficiency by including near infrared light region as a basic structure of
HAD (Hole-Accumulation-Diode) sensor.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E99525A99
ICX259AK
Block Diagram and
Pin Configuration
(Top View)
V
OUT
GND
Vφ
1
Vφ
3
2
Ye
G
Ye
Mg
Ye
G
8
7
6
5
Vφ
2
4
3
Cy
Ye
G
Ye
Mg
Ye
G
Cy
Mg
Cy
G
Cy
Mg
Vertical Register
Mg
Cy
G
Cy
Mg
Horizontal Register
Note)
: Photo sensor
9
10
11
12
13
14
15
16
GND
φSUB
φRG
Hφ
1
V
DD
Pin Description
Pin No.
1
2
3
4
5
6
7
8
Symbol
Vφ
4
Vφ
3
Vφ
2
Vφ
1
GND
NC
NC
V
OUT
Signal output
Description
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
Vertical register transfer clock
GND
Pin No.
9
10
11
12
13
14
15
16
Hφ
2
V
L
NC
Vφ
4
1
Note)
NC
NC
Symbol
V
DD
GND
φSUB
V
L
φRG
NC
Hφ
1
Hφ
2
Description
Supply voltage
GND
Substrate clock
Protective transistor bias
Reset gate clock
Horizontal register transfer clock
Horizontal register transfer clock
Absolute Maximum Ratings
Item
V
DD
, V
OUT
,
φRG
–
φSUB
Against
φSUB
Vφ
1
, Vφ
3
–
φSUB
Vφ
2
, Vφ
4
, V
L
–
φSUB
Hφ
1
, Hφ
2
, GND –
φSUB
V
DD
, V
OUT
,
φRG
– GND
Against GND
Vφ
1
, Vφ
2
, Vφ
3
, Vφ
4
– GND
Hφ
1
, Hφ
2
– GND
Against V
L
Vφ
1
, Vφ
3
– V
L
Vφ
2
, Vφ
4
, Hφ
1
, Hφ
2
, GND – V
L
Voltage difference between vertical clock input pins
Between input clock
pins
Storage temperature
Operating temperature
∗
1
+24V (Max.) when clock width < 10µs, clock duty factor < 0.1%.
–2–
Hφ
1
– Hφ
2
Hφ
1
, Hφ
2
– Vφ
4
Ratings
–40 to +8
–50 to +15
–50 to +0.3
–40 to +0.3
–0.3 to +20
–10 to +18
–10 to +6
–0.3 to +28
–0.3 to +15
to +15
–6 to +6
–14 to +14
–30 to +80
–10 to +60
Unit
V
V
V
V
V
V
V
V
V
V
V
V
°C
°C
∗
1
Remarks
ICX259AK
Bias Conditions
Item
Supply voltage
Protective transistor bias
Substrate clock
Reset gate clock
Symbol
V
DD
V
L
φSUB
φRG
Min.
14.55
Typ.
15.0
∗
1
∗
2
∗
2
Max.
15.45
Unit
V
Remarks
∗
1
V
L
setting is the V
VL
voltage of the vertical transfer clock waveform, or the same power supply as the V
L
power supply for the V driver should be used.
∗
2
Do not apply a DC bias to the substrate clock and reset gate clock pins, because a DC bias is generated
within the CCD.
DC Characteristics
Item
Supply current
Symbol
I
DD
Min.
Typ.
4
Max.
6
Unit
mA
Remarks
Clock Voltage Conditions
Item
Readout clock voltage
Symbol
V
VT
V
VH1
, V
VH2
V
VH3
, V
VH4
V
VL1
, V
VL2
,
V
VL3
, V
VL4
Vφ
V
Vertical transfer clock
voltage
V
VH3
– V
VH
V
VH4
– V
VH
V
VHH
V
VHL
V
VLH
V
VLL
Horizontal transfer
clock voltage
Vφ
H
V
HL
Vφ
RG
Reset gate clock
voltage
V
RGLH
– V
RGLL
V
RGL
– V
RGLm
Substrate clock voltage Vφ
SUB
21.0
22.0
4.75
–0.05
4.5
5.0
0
5.0
Min.
14.55
–0.05
–0.2
–8.0
6.3
–0.25
–0.25
Typ.
15.0
0
0
–7.0
7.0
Max.
15.45
0.05
0.05
–6.5
8.05
0.1
0.1
0.3
0.3
0.3
0.3
5.25
0.05
5.5
0.4
0.5
23.5
Unit
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Waveform
diagram
1
2
2
2
2
2
2
2
2
2
2
3
3
4
4
4
5
Input through 0.1µF
capacitance
Low-level coupling
Low-level coupling
High-level coupling
High-level coupling
Low-level coupling
Low-level coupling
V
VL
= (V
VL3
+ V
VL4
)/2
Vφ
V
= V
VH
n – V
VL
n (n = 1 to 4)
V
VH
= (V
VH1
+ V
VH2
)/2
Remarks
–3–
ICX259AK
Clock Equivalent Circuit Constant
Item
Capacitance between vertical transfer
clock and GND
Symbol
Cφ
V1
, Cφ
V3
Cφ
V2
, Cφ
V4
Cφ
V12
, Cφ
V34
Capacitance between vertical transfer
clocks
Cφ
V23
, Cφ
V41
Cφ
V13
Cφ
V24
Capacitance between horizontal
transfer clock and GND
Capacitance between horizontal
transfer clocks
Capacitance between reset gate clock
and GND
Capacitance between substrate clock
and GND
Vertical transfer clock series resistor
Vertical transfer clock ground resistor
Horizontal transfer clock series resistor
Reset gate clock series resistor
Vφ
1
Cφ
V12
Min.
Typ.
1200
1000
680
330
100
100
75
30
5
270
82
120
100
15
50
Max.
Unit
pF
pF
pF
pF
pF
pF
pF
pF
pF
pF
Ω
Ω
Ω
Ω
Ω
Remarks
Cφ
H1
, Cφ
H2
Cφ
HH
Cφ
RG
Cφ
SUB
R
1
, R
3
R
2
, R
4
R
GND
Rφ
H
Rφ
RG
Vφ
2
R
1
R
2
Rφ
H
Hφ
1
Rφ
H
Hφ
2
Cφ
HH
Cφ
V23
Cφ
V13
Cφ
H1
Cφ
H2
Cφ
V1
Cφ
V41
Cφ
V24
Cφ
V2
Cφ
V4
R
GND
Cφ
V3
R
4
Cφ
V34
R
3
Vφ
4
Vφ
3
Vertical transfer clock equivalent circuit
Rφ
RG
RGφ
Horizontal transfer clock equivalent circuit
Cφ
RG
Reset gate clock equivalent circuit
–4–
Analog electronics
京公网安备 11010802033920号
EEWORLD
