NanoAmp Solutions, Inc.
670 North McCarthy Blvd. Suite 220, Milpitas, CA 95035
ph: 408-935-7777, FAX: 408-935-7770
www.nanoamp.com
N16D1633LPA
Advance Information
512K × 16 Bits × 2 Banks Low Power Synchronous DRAM
DESCRIPTION
These N16D1633LPA are low power 16,777,216 bits CMOS Synchronous DRAM organized as 2 banks of 524,288
words x 16 bits. These products are offering fully synchronous operation and are referenced to a positive edge of the
clock. All inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally
pipelined to achieve very high bandwidth. All input and output voltage levels are compatible with LVTTL.
Features
• JEDEC standard 3.0V/3.3V power supply.
• Auto refresh and self refresh.
• All pins are compatible with LVTTL interface.
• 4K refresh cycle / 64ms.
• Programmable Burst Length and Burst Type.
- 1, 2, 4, 8 or Full Page for Sequential Burst.
- 4 or 8 for Interleave Burst.
• Programmable CAS Latency : 2,3 clocks.
• Programmable Driver Strength Control.
- Full Strength or 1/2, 1/4 of Full Strength
• Deep Power Down Mode
• All inputs and outputs referenced to the positive
edge of the system clock.
• Data mask function by DQM.
• Internal dual banks operation.
• Burst Read Single Write operation.
• Special Function Support.
-PASR (Partial Array Self Refresh)
-Auto TCSR(Temperature Compensated Self Refresh)
• Automatic precharge, includes CONCURRENT
Auto Precharge Mode and controlled Precharge
Table 1: Ordering Information
PART NO.
N16D1633LPAZ2-75I
N16D1633LPAZ2-10I
N16D1633LPAC2-60I
N16D1633LPAC2-75I
N16D1633LPAC2-10I
N16D1633LPAT2-60I
N16D1633LPAT2-75I
N16D1633LPAT2-10I
CLOCK Freq.
133MHz
100MHz
166MHz
133MHz
100MHz
166MHz
133MHz
100MHz
-25
o
C to
85
o
C
3.0V/3.0V
or
3.3V/3.3V
Temperature
VDD/VDDQ
INTERLEAVE
PACKAGE
48-Ball Green
FBGA
60-Ball Green
WBGA
50-Pin Green
TSOP II
LVTTL
Stock No. 23395- Rev L 1/06
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
1
N16D1633LPA
NanoAmp Solutions, Inc.
Advance Information
Table 2: Pin Descriptions
PIN
CLK
CKE
/CS
A11
A0~A10
PIN NAME
System Clock
Clock Enable
Chip Select
Bank Address
Address
Row Address Strobe,
Column Address Strobe,
Write Enable
Data Input/Output Mask
Data Input/Output
Power Supply/Ground
Data Output Power/Ground
No Connection
DESCRIPTIONS
The system clock input. All other inputs are registered to the
SDRAM on the rising edge of the CLK
Controls internal clock signal and when deactivated, the
SDRAM will be one of the states among power down, suspend
or self refresh.
Enable or disable all inputs except CLK, CKE and DQM
Selects bank to be activated during /RAS activity
Selects bank to be read/written during /CAS activity
Row Address : RA0~RA10
Column Address: CA0~CA7
Auto Precharge : A10
/RAS, /CAS and /WE define the operation
Refer function truth table for details
Controls output buffers in read mode and masks input data in
write mode
Multiplexed data input/output pin
Power supply for internal circuits and input buffers
Power Supply for output buffers
No Connection
/RAS, /CAS, /WE
LDQM/UDQM
DQ0~DQ15
VDD/VSS
VDDQ/VSSQ
NC
Stock No. 23395- Rev L 1/06
The specifications of this device are subject to change without notice. For latest documentation see http://www.nanoamp.com.
5
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