IS63LV1024
128K x 8 HIGH-SPEED CMOS STATIC RAM
3.3V REVOLUTIONARY PINOUT
FEATURES
• High-speed access times:
8, 10, 12 and 15 ns
• High-performance, low-power CMOS process
• Multiple center power and ground pins for
greater noise immunity
• Easy memory expansion with
CE
and
OE
options
•
CE
power-down
• Fully static operation: no clock or refresh
required
• TTL compatible inputs and outputs
• Single 3.3V power supply
• Packages available:
– 32-pin 300-mil SOJ
– 32-pin 400-mil SOJ
– 32-pin TSOP (Type II)
ISSI
DESCRIPTION
®
SEPTEMBER 2000
The
ISSI
IS63LV1024 is a very high-speed, low power,
131,072-word by 8-bit CMOS static RAM in revolutionary
pinout. The IS63LV1024 is fabricated using
ISSI
's
high-performance CMOS technology. This highly reliable
process coupled with innovative circuit design
techniques, yields higher performance and low power
consumption devices.
When
CE
is HIGH (deselected), the device assumes a
standby mode at which the power dissipation can be
reduced down to 250 µW (typical) with CMOS input levels.
The IS63LV1024 operates from a single 3.3V power
supply and all inputs are TTL-compatible.
FUNCTIONAL BLOCK DIAGRAM
A0-A16
DECODER
128K X 8
MEMORY ARRAY
VCC
GND
I/O
DATA
CIRCUIT
I/O0-I/O7
COLUMN I/O
CE
OE
WE
CONTROL
CIRCUIT
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any
errors which may appear in this publication. © Copyright 2000, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
1
IS63LV1024
PIN CONFIGURATION
32-Pin SOJ
ISSI
PIN CONFIGURATION
32-Pin TSOP (Type II) (T)
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A16
A15
A14
A13
OE
I/O7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
®
A0
A1
A2
A3
CE
I/O0
I/O1
Vcc
GND
I/O2
I/O3
WE
A4
A5
A6
A7
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A16
A15
A14
A13
OE
I/o7
I/O6
GND
Vcc
I/O5
I/O4
A12
A11
A10
A9
A8
PIN DESCRIPTIONS
A0-A16
CE
OE
WE
I/O0-I/O7
Vcc
GND
Address Inputs
Chip Enable Input
Output Enable Input
Write Enable Input
Bidirectional Ports
Power
Ground
TRUTH TABLE
Mode
WE
CE
H
L
L
L
OE
X
H
L
X
I/O Operation Vcc Current
High-Z
High-Z
D
OUT
D
IN
I
SB
1
, I
SB
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
I
CC
1
, I
CC
2
Not Selected
X
(Power-down)
Output Disabled H
Read
H
Write
L
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
T
BIAS
T
STG
P
T
Parameter
Terminal Voltage with Respect to GND
Temperature Under Bias
Storage Temperature
Power Dissipation
Value
–0.5 to Vcc + 0.5
–55 to +125
–65 to +150
1.0
Unit
V
°C
°C
W
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
IS63LV1024
OPERATING RANGE
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
–40°C to +85°C
V
CC
3.3V ± 0.3V
3.3V ± 0.15V
ISSI
®
DC ELECTRICAL CHARACTERISTICS
(Over Operating Range)
Symbol Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
I
LO
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
(1)
Input Leakage
Output Leakage
GND
≤
V
IN
≤
V
CC
GND
≤
V
OUT
≤
V
CC
, Outputs Disabled
Com.
Ind.
Com.
Ind.
Test Conditions
V
CC
= Min., I
OH
= –4.0 mA
V
CC
= Min., I
OL
= 8.0 mA
Min.
2.4
—
2.2
–0.3
–1
–5
–1
–5
Max.
—
0.4
V
CC
+ 0.3
0.8
1
5
1
5
Unit
V
V
V
V
µA
µA
Notes:
1. V
IL
= –3.0V for pulse width less than 10 ns.
POWER SUPPLY CHARACTERISTICS
(1)
(Over Operating Range)
Symbol Parameter
I
CC
1
I
SB
Vcc Operating
Supply Current
TTL Standby
Current
(TTL Inputs)
TTL Standby
Current
(TTL Inputs)
CMOS Standby
Current
(CMOS Inputs)
Test Conditions
V
CC
= Max.,
CE
= V
IL
I
OUT
= 0 mA, f = Max.
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = Max
V
CC
= Max.,
V
IN
= V
IH
or V
IL
CE
≥
V
IH
, f = 0
V
CC
= Max.,
CE
≤
V
CC
– 0.2V,
V
IN
≥
V
CC
– 0.2V, or
V
IN
≤
0.2V, f = 0
Com.
Ind.
Com.
Ind.
Com.
Ind.
Com.
Ind.
-8 ns
Min. Max.
—
—
—
—
—
—
—
—
160
170
55
55
25
30
5
10
-10 ns
Min. Max.
—
—
—
—
—
—
—
—
150
160
45
45
25
30
5
10
-12 ns
Min. Max.
—
—
—
—
—
—
—
—
130
140
40
40
25
30
5
10
-15 ns
Min. Max.
—
—
—
—
—
—
—
—
120
130
35
35
25
30
5
10
Unit
mA
mA
I
SB
1
mA
I
SB
2
mA
Notes:
1. At f = f
MAX
, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change.
CAPACITANCE
(1,2)
Symbol
C
IN
C
I/O
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
V
IN
= 0V
V
OUT
= 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: T
A
= 25°C, f = 1 MHz, Vcc = 3.3V.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
3
IS63LV1024
READ CYCLE SWITCHING CHARACTERISTICS
(1)
(Over Operating Range)
Symbol
Parameter
Read Cycle Time
Address Access Time
Output Hold Time
CE
Access Time
OE
Access Time
OE
to Low-Z Output
CE
to Low-Z Output
CE
to Power Up Time
CE
to Power Down Time
-8 ns
Min.
Max.
8
—
2
—
—
0
0
3
0
0
—
—
8
—
8
4
—
4
—
4
—
8
-10 ns
Min.
Max.
10
—
2
—
—
0
0
3
0
0
—
—
10
—
10
5
—
5
—
5
—
10
-12 ns
Min.
Max.
12
—
3
—
—
0
0
3
0
0
—
—
12
—
12
6
—
6
—
6
—
12
ISSI
-15 ns
Min.
Max.
15
—
3
—
—
0
0
3
0
0
—
—
15
—
15
7
—
7
—
7
—
15
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
(2)
t
LZCE
(2)
t
PU
t
PD
t
HZOE
(2)
OE
to High-Z Output
t
HZCE
(2)
CE
to High-Z Output
Notes:
1. Test conditions assume signal transition times of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and C1
output loading specified in Figure 1.
2. Tested with the C2 load in Figure 1. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing
and Reference Levels
Output Load
Unit
0V to 3.0V
3 ns
1.5V
See Figures 1a and 1b
AC TEST LOADS
317
Ω
3.3V
Z
OUT
= 50
Ω
OUTPUT
50
Ω
V
T
= 1.5V
OUTPUT
5 pF
Including
jig and
scope
351
Ω
Figure 1
Figure 2
4
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
IS63LV1024
AC WAVEFORMS
READ CYCLE NO. 1
(1,2)
t
RC
ADDRESS
ISSI
®
t
AA
t
OHA
D
OUT
PREVIOUS DATA VALID
t
OHA
DATA VALID
READ1.eps
READ CYCLE NO. 2
(1,3)
t
RC
ADDRESS
t
AA
OE
t
OHA
t
DOE
CE
t
HZOE
t
LZOE
t
ACE
t
LZCE
t
HZCE
DATA VALID
CE_RD2.eps
D
OUT
HIGH-Z
Notes:
1.
WE
is HIGH for a Read Cycle.
2. The device is continuously selected.
OE, CE
= V
IL
.
3. Address is valid prior to or coincident with
CE
LOW transitions.
Integrated Silicon Solution, Inc. — 1-800-379-4774
Rev. H
10/02/00
5
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