MachXO™ Standard Evaluation Board - Revisions 001 & 002
User’s Guide
March 2008
Revision: EB21_01.6
Lattice Semiconductor
MachXO Standard Evaluation Board
Revisions 001 & 002 User’s Guide
Introduction
The MachXO Standard Evaluation board provides a convenient platform to evaluate electrical characteristics of the
MachXO device, and to evaluate, test and de-bug custom logic designs. The board features a MachXO device in a
256-ball fpBGA package. The MachXO I/Os are connected to a rich variety of interfaces, including an 8-bit input
switch, LEDs, PCB test points, 0.10” general purpose headers and optional high-speed SMA connectors. The
board includes selectable power for mixed core I/O voltage operation. A 33MHz oscillator, as well as an ispClock™
PLL synthesis device are also included on the board.
Features
• MachXO in 256-ball fine pitch Ball Grid Array package (MachXO640 or MachXO2280)
• Single printed circuit board solution
• Eight LEDs for visual feedback
• 8-bit input switch
• General purpose push-button
• 1149.1 JTAG programming/boundary-scan interface
• Built-in power supply operating with an DC input between 5V and 20V
• Selectable CORE voltage for the MachXO
• Selectable voltages for a portion of the I/O banks
• Built-in adjustable oscillator for reference clocking source
• Lattice ispClock5610 multiple output PLL
• SMA connector landing pads (SMA connectors not populated) to MachXO clock input/general purpose I/O pins
• RJ-45 connector (not populated)
• LCD/GPIO footprint
• 100mil center-center test point grid
• Impedance controlled Mictor (not populated)
General Description
The heart of the board is the MachXO programmable logic device in a 256-ball fpBGA package. The board is
designed to cover a broad range of core and I/O voltage requirements. The MachXO “C” grade devices require a
core voltage supply between 1.5V to 3.3V and an auxiliary 3.3V supply. The “E” grade devices require a core volt-
age supply at 1.2V and an auxiliary I/O supply at 3.3V. The MachXO Standard Evaluation Board provides three
supply voltages, all sourced from a 5V to 20V external source (or sourced individually via the banana jack inputs).
The board provides fixed 1.2V and 3.3V power rails and a single adjustable voltage that ranges from 1.2V to 3.3V.
It is possible to use external power supplies to override the fixed output levels if desired. The voltage supplied to the
MachXO core is selectable. The core voltage is changed by moving a single current sense resistor.
Once a correct set of supply voltages has been applied to the MachXO, the device can be programmed. The
MachXO can be programmed and verified with a Lattice JTAG download cable, which should be connected to the
1x10 SIP header on the board (1149.1 JTAG interface). The ispVM
®
System software controls the programming
and verification process. The ispVM System software is available for download from www.latticesemi.com/software.
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Lattice Semiconductor
MachXO Standard Evaluation Board
Revisions 001 & 002 User’s Guide
The evaluation board also includes a Lattice ispClock5610. This part is also programmed using the same JTAG
interface. The ispClock5610 can be used to generate synthesized clock inputs to the MachXO device.
The evaluation board includes additional components to aid in evaluating the MachXO PLD. These are described in
the following sections in more detail.
Additional Resources
Additional resources related to this board can be downloaded from the web at www.latticesemi.com/boards. Click
on the appropriate evaluation board, then see the blue “Resources” box on the right of the screen for items such as:
updated documentation, downloadable software, sample designs and more.
Getting Started
In order to use the MachXO Standard Evaluation Board, it must first be powered. Follow the guidelines in the
Power Supply section below for details.
The MachXO Standard Evaluation Board is shipped from the factory pre-configured with a sample program loaded
in both the MachXO and ispClock devices. The source code and programming files are available for download from
the Lattice web site at: www.latticesemi.com/boards. The sample programs operate as follows.
MachXO: Setting all of the 8-bit input switches to ON causes the associated LEDs to count in one direction (8-bit
binary counter). Setting all of the 8-bit input switches to OFF reverses the direction of the count. If the switches are
not all ON or all OFF, the LEDs for the switches that are ON will light up. Additionally, other I/Os on the MachXO
device are also toggled using the internal counter outputs. See the source code and preference file available on-
line for more information.
ispClock5610: The ispClock5610 sample program generates a 33MHz clock input to the MachXO device.
To reprogram the board, you will need the following items:
•
ispLEVER Software:
HDL design support for the MachXO device is included in both ispLEVER 5.0 SP1 and
downloadable ispLEVER-Starter 5.0 SP1 (or later) software tools
•
ispVM System:
This is the Lattice programming management tool which is used to download custom ispLEVER
designs from your PC to the MachXO device via an ispDOWNLOAD
®
cable. The ispVM System software is avail-
able for download from the Lattice web site at: www.latticesemi.com/ispvm.
•
ispDOWNLOAD Cable:
An ispDOWNLOAD Cable is required to connect your PC to the MachXO Standard
Evaluation Board. ispDOWNLOAD Cables are available for purchase separately from the Lattice on-line store
(www.latticesemi.com/store) or any Lattice distributor. For more information see:
www.latticesemi.com/products/devtools/hardware/ispdownload/
MachXO Standard Evaluation Board Functional Description
The MachXO Standard Evaluation Board is comprised of several primary functional blocks as shown in Figure 1. In
the descriptions below, locations of components and board features are described relative to a compass symbol
placed adjacent to the Lattice Semiconductor logo. For example, the DIP oscillator is on the southwest corner of
the board, and the Lattice logo is on the northeast corner of the board.
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Lattice Semiconductor
Figure 1. MachXO Standard Evaluation Board
JTAG Programming
Interface
Prototype
Area
MachXO Standard Evaluation Board
Revisions 001 & 002 User’s Guide
LCD Display
Area
Power
Inputs
West
North
East
South
RJ-45
Connector
Area
SMA
Connector
Area
DC Power
Input Jack
ispClock5610
DIP Oscillator
Push-Button
Switches
8-Bit Input
Switch
Prototype
Areas
Power Supply
The MachXO Standard Evaluation Board includes two locations to apply power. On the east side of the board are a
pair of banana jacks (JP28 and JP29) and a coaxial DC connector (JP30), which receive power from either a bench
power supply or a brick style power supply. A DC source between 5.0V and 28.0V must be applied in order to
power the board. The coaxial DC connector uses a 2.5mm central pin, with a 6.3mm outer diameter barrel.
The output from the DC system is controlled by switch S5. Switch S5 is in the southeast corner of the board. This is
a small surface mount switch that enables and disables the LTC1775 DC-DC conversion chip. The output voltages
from the power supply are enabled when the switch is in the “on” position.
The 5.0V to 28.0V DC input voltage is converted by DC-DC converters and switching power supplies to provide
3.3V, 1.2V, and an adjustable DC source on the board. The output from these supplies travels through surface
mounted fuse holders. Fuses are supplied and prevent over-current conditions from damaging the components on
the board (Vendor: Littlefuse, Make: Nano SMF Very Fast Acting, 1.5A or 3A).
Due west of the fuse blocks are more banana plug connectors. These connectors provide an alternate means for
applying DC voltage levels to the board. To apply voltages not supplied by the on-board power section,
first
remove the appropriate fuse from the fuse holder
. Then connect an alternate DC supply to the banana plug
connector associated with that fuse.
Table 1. Power Supply Fuses
Fuse Number
F1
F2
F3
Supply Rail
Enabled/Disabled
V
ADJ
1.2V
3.3V
Banana Connector
Input
JP25
JP26
JP27
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Lattice Semiconductor
MachXO Standard Evaluation Board
Revisions 001 & 002 User’s Guide
Adjacent to JP25-27 are current sense resistors. These permit the measurement of the current flowing from each
of the power supplies. A single resistor can be moved to permit 1.2V, 3.3V, or V
ADJ
to supply V
CORE
to the MachXO.
Table 2. MachXO Core Voltage Selection
Resistor
R141
R142
R144
Voltage Supplied
to the MachXO Core
V
ADJ
1.2V
3.3V
The remaining current sense resistors permit the measurement of the V
CCIO
current draw.
Table 3. MachXO I/O Voltage Rails
Resistor
R143
R145
R148
I/O Bank Voltage
1.2V
3.3V
V
ADJ
Four V
CCIO
banks are available on the MachXO Standard Evaluation board. Three of the four I/O banks can be
selected. V
CCIO2
is always powered at 3.3V. This forces the JTAG interface to run at 3.3V. V
CCIO0
, V
CCIO1
, and
V
CCIO3
can be altered using jumpers.
Table 4. MachXO I/O Voltage Selection
Jumper Block
JP20
V
CCIO
Controlled
1-2: V
CCIO1
= 3.3V
3-4: V
CCIO1
= V
ADJ
5-6: V
CCIO1
= 1.2V
1-2: V
CCIO0
= 3.3V
3-4: V
CCIO0
= V
ADJ
5-6: V
CCIO0
= 1.2V
1-2: V
CCIO3
= 3.3V
3-4: V
CCIO3
= V
ADJ
5-6: V
CCIO3
= 1.2V
JP21
JP22
Figure 2. MachXO Standard Evaluation Board
Pin 6
Pin 1
Programmability
The programming interface for the MachXO (and ispClock5610) is located in the northwest corner of the board.
The 1x10 header, JP7, is the connection point for the JTAG download cable. Jumpers JP6 and JP8 determine how
the TDI/TDO chain and TMS pins behave.
Important Note:
The board must be un-powered when connecting, disconnecting, or reconnecting the ispDOWN-
LOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG
pins. Failure to follow these procedures can in result in damage to the MachXO device and render the board inop-
erable.
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